Mixed Signal Verification Engineer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, AMS Designer, Verilog-AMS/VHDL-AMS, real-number modeling, Python, regression infrastructure

About the role

You will own mixed-signal verification at a fabless semiconductor company, building the testbenches and methodologies that prove analog and digital work together before tapeout. The team writes UVM environments with real-number models, AMS assertions, and regressions that catch the interface bugs transistor-level simulation is too slow to find. This role matters because you are the last line of defense: the bugs you catch in simulation never become respins. You will partner with analog designers to understand intended behavior deeply enough to write checkers that catch real bugs, and with the digital verification team to keep the AMS regression green on every database drop.

What you will achieve

Build UVM-based mixed-signal testbenches for two to three analog subsystems per year, with real-number models, functional coverage, and assertions that run in the standard regression.
Drive bug-finding before tapeout: your testbenches will catch interface bugs (clock domain crossings, reset sequencing, power-mode transitions, calibration handshakes) that block-level simulation misses.
Reduce AMS regression runtime by developing and maintaining accurate real-number models of analog blocks, trading model fidelity against speed with documented accuracy budgets.
Own the mixed-signal regression: define the test plan, triage failures to real bugs versus testbench issues, and report coverage and bug-rate metrics to the tapeout readiness review.
Cut respin risk from analog-digital interaction by writing AMS assertions for interface protocols (handshakes, timing, voltage levels) that flag violations automatically in every regression run.

What you will bring

Must-haves

2-5 years in mixed-signal or analog verification with UVM testbench experience on your record.
Fluency in SystemVerilog and UVM: agents, sequences, scoreboards, and coverage applied to mixed-signal DUTs.
Ability to write and debug real-number models (SystemVerilog RNM, Verilog-AMS, or wreal) that capture analog behavior accurately enough to find bugs.
Understanding of analog fundamentals sufficient to verify them: you can read a datasheet spec and write a checker for it.
Experience with AMS simulators (AMS Designer, CustomSim, or equivalent) and mixed-signal regression flows.
Debug discipline: distinguishing DUT bugs from testbench bugs quickly and documenting both clearly.

Nice-to-haves

Familiarity with formal verification techniques applied to analog-digital interfaces.
Experience with power-aware verification (UPF) in mixed-signal contexts.
Knowledge of analog DFT/BIST and how to verify it.