Memory IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SRAM/DRAM macros, sense amplifiers, bitcells, memory compilers, redundancy and repair, low-Vmin design, Cadence Virtuoso, Spectre, NanoTime

About the role

You will join a memory semiconductor company designing embedded and standalone memory macros that ship inside customer SoCs and memory products. The team owns the full memory subsystem: bitcells, sense amps, decoders, redundancy, and the timing that makes it all work at speed. This role matters because memory area, power, and Vmin directly set the PPA of every SoC it goes into, and a single weak bitcell can scrap a million-unit product. Memory bitcells scale harder than logic, and each node brings new variation challenges to solve. Memory teams run lean and deep, and your bitcell expertise will be central to every program.

What you will achieve

Ship memory macros that meet density, access-time, and power targets on first silicon across process corners and voltage ranges
Design sense amplifiers and bitcell arrays that hold read stability and write margin down to the product's minimum operating voltage
Cut Vmin through assist techniques and variation-tolerant design, extending battery life and yield for customer SoCs
Deliver redundancy and repair schemes (row/column redundancy, ECC) that recover yield without blowing the area budget
Drive memory compiler development or macro hardening flows that let digital teams integrate your macros with push-button reliability
Own silicon shmoo and characterization, correlating measured Vmin and timing against simulation across temperature
Evaluate emerging memory technologies and prototype arrays that could become future product lines

What you will bring

Must-haves

2-5 years designing memory circuits with shipped SRAM, DRAM, or embedded memory products
Deep understanding of bitcell operation: read stability, write margin, half-select disturb, and leakage in scaled nodes
Design experience with sense amplifiers, wordline drivers, column muxes, or timing and control logic for memories
Familiarity with redundancy, repair, and ECC schemes and their area and test tradeoffs
Proficiency in Cadence Virtuoso and Spectre, including statistical analysis for bitcell yield estimation
Working knowledge of memory test: BIST, shmoo plotting, and failure analysis of weak cells
B.S. or M.S. in Electrical Engineering with a circuits or memory design focus

Nice-to-haves

Experience with emerging memories: MRAM, RRAM, or FeRAM design considerations
Familiarity with high-bandwidth or low-latency memory interfaces (HBM, GDDR)
Prior work on memory compilers or automated macro generation flows