Machine Learning Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, ML accelerator datapaths, tensor unit verification, numerical checking (FP/INT quantization), dataflow architectures, Python/NumPy reference models

About the role

You will verify machine learning accelerators at a semiconductor company where the product is measured in tera-operations per second and numerical exactness. Working with ML architects and RTL designers, you will prove that matrix engines, tensor units, and dataflow fabrics compute correctly across precisions, sparsity patterns, and tiling strategies. Your numerical checkers decide whether the accelerator's math can be trusted in production models, and your reference models are the ground truth. When a deployed model silently degrades because the accelerator's math drifted, the failure is invisible until it is expensive, which is why your numerical rigor matters more than raw coverage numbers.

What you will achieve

Deliver bit-accurate reference models in Python/NumPy for accelerator datapaths, integrated into UVM scoreboards that check every computed tensor against golden results.
Drive numerical coverage across precisions (FP32, FP16, BF16, INT8, INT4), rounding modes, and sparsity patterns to the targets set with architects.
Ship verification of dataflow and tiling behavior proving correct results under all legal memory access patterns and buffer sizes.
Cut debug time on numerical mismatches by building precision-aware comparison with configurable tolerance and automatic failing-operation isolation.
Reduce model-accuracy risk by running representative neural-network layers through the verified design and comparing against golden framework outputs end to end.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with datapath-heavy or compute-intensive designs.
Strong SystemVerilog/UVM skills plus solid Python for building numerical reference models you trust.
Understanding of ML accelerator architecture: systolic arrays, tensor cores, dataflow styles, and on-chip memory hierarchies.
Knowledge of numerical formats and their pitfalls: quantization, rounding, overflow, saturation, and precision loss.
Experience verifying complex datapaths with self-checking, transaction-level comparison at scale.
Ability to work with architects on the verification implications of new data types and sparsity support.
Numerical discipline: you know the difference between a tolerable rounding difference and a real bug, and you prove it.

Nice-to-haves

Familiarity with ML frameworks (PyTorch, TensorFlow) for generating golden test vectors.
Experience with formal verification of arithmetic units.
Knowledge of interconnect or NoC verification for multi-core accelerator fabrics.
Exposure to sparsity, pruning, or mixed-precision training concepts that shape test content.