Low Power Mixed Signal Engineer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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Texas Instruments

Analog Devices

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Marvell

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The job description

Tech stack. Cadence Virtuoso, Spectre, UPF power intent, Verilog-AMS, MATLAB, Python, ultra-low-power design flows

About the role

You will design ultra-low-power mixed-signal circuits at a fabless semiconductor company building battery-powered chips that must run for years on a coin cell. The team treats every nanoamp as a design variable: subthreshold amplifiers, duty-cycled references, and event-driven architectures that sip power in sleep and wake fast. This role matters because battery life is the product spec customers feel most directly, and your circuits decide it. You will work across the stack with digital, firmware, and packaging, because in ultra-low-power design the system architecture and the circuit techniques have to be invented together.

What you will achieve

Ship ultra-low-power analog blocks (subthreshold amplifiers, nanoamp references, comparators, or low-power ADCs) that meet their power budgets: sleep currents in the nanoamp range and active power at or under allocation.
Drive system battery life by co-optimizing with the digital and firmware teams: duty cycling, power gating, and wake-up latency tradeoffs that extend measured battery life by 20% or more versus the prior generation.
Reduce leakage impact through circuit and layout technique: power switches, body biasing, and high-Vt device strategies that hold standby current across temperature corners.
Own power modeling for your blocks: spreadsheet and MATLAB models of active, sleep, and transition energy that predict measured battery life within 10% before tapeout.
Cut power-related surprises by verifying power intent: UPF-driven simulation of power domains, isolation, and retention, plus silicon measurement of every power mode in the lab.

What you will bring

Must-haves

2-5 years designing low-power or ultra-low-power analog/mixed-signal circuits with tapeout and measured power results.
Deep understanding of subthreshold operation: gm/Id design methodology, weak inversion tradeoffs, and the noise and matching penalties of low-current design.
Experience with power management at the block level: power gating, multiple supply domains, retention, and wake-up sequencing.
Fluency in leakage analysis: subthreshold, gate, and junction leakage across corners and temperature, and techniques to control each.
Familiarity with UPF power intent and low-power simulation methodology.
Lab skills for low-power measurement: picoamp-level current measurement and power-mode characterization.

Nice-to-haves

Experience with energy harvesting interfaces or battery management circuits.
Knowledge of duty-cycled architectures and event-driven wake-up design.
Familiarity with wireless sensor or IoT system power budgets.