Lead Mixed Signal Design Engineer

About the role

You will lead a small team of analog and mixed-signal designers at a fabless semiconductor company, owning both the technical output and the schedule of the analog subsystem. Leads here still design: you will carry the hardest block yourself while making sure four or five other designers hit their tapeout milestones. This role matters because the analog subsystem is on the critical path of the chip, and your leadership decides whether it arrives excellent and on time or late and compromised. You will also run the analog tapeout readiness reviews where every block owner defends simulation coverage, layout quality, and ESD protection before the design is released to the foundry.

What you will achieve

• Deliver the complete analog/mixed-signal subsystem on the tapeout schedule: partition the work, set milestones, track block-level progress weekly, and remove technical blockers before they slip.
• Design the most technically demanding block in the subsystem yourself (high-speed ADC, precision PLL, or equivalent), meeting its spec with margin and full sign-off documentation.
• Cut schedule risk by running structured design reviews at architecture, schematic, layout, and pre-tapeout stages, with written action items and clear ownership for every issue found.
• Build a team that ships: hire strong designers, give direct technical feedback, and develop each team member toward independent block ownership within their first year.
• Reduce respin risk for the subsystem by enforcing a single sign-off standard (extracted corners, Monte Carlo, EM/IR, ESD/latch-up) across every block, with you as the final reviewer.

What you will bring

Must-haves

• 7-10+ years of analog/mixed-signal design with multiple successful tapeouts and deep expertise in at least one analog domain.
• Prior technical leadership: leading a small team, a subsystem, or a multi-block tapeout effort with real schedule accountability.
• Ability to carry the hardest design problem while managing others: you can still do transistor-level design at a senior level.
• Strong planning instincts: breaking a subsystem into blocks, estimating effort honestly, sequencing dependencies, and communicating status clearly.
• Experience hiring, mentoring, and giving direct performance feedback to analog designers.
• Full sign-off fluency so you can be the final technical reviewer for every block your team tapes out.

Nice-to-haves

• Experience leading teams across sites or time zones.
• Familiarity with project tracking tools and lightweight agile practices adapted to silicon schedules.
• Advanced-node tapeout experience as a lead.