Lead Analog IC Design Engineer

Analog IC Design Engineer Lead, technical leadership of a small team 7-10+ years

Other levels: Analog IC Design Engineer Senior Analog IC Design Engineer Principal Analog IC Design Engineer Staff Analog IC Design Engineer Junior Analog IC Design Engineer

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Qualcomm

Texas Instruments

Analog Devices

Broadcom

Skyworks

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The job description

Tech stack. Team technical leadership, Cadence Virtuoso, Spectre, tapeout program management, design review leadership, milestone and risk tracking

About the role

You will join an analog IP startup as the lead analog IC design engineer, the technical owner of a small design team building the company's core analog portfolio. You will still design: this is a player-coach role where your own blocks are often the most critical ones on the die. This role matters because the startup's valuation rests on analog IP that must be best-in-class on first silicon; your team is the engine, and you set its pace and its quality bar.

What you will achieve

Deliver the analog IP portfolio on schedule, running a team of three to six designers through architecture, design, layout, and validation
Personally design the highest-risk blocks on the roadmap, proving by example the quality standard the team must meet
Drive tapeout execution: milestone plans, risk registers, and review gates that keep multiple blocks converging on the same schedule
Build a review culture where designs arrive hardened: your team will have the lowest ECO rate in the company within two tapeout cycles
Grow the team deliberately, hiring and onboarding designers who raise the bar and retain the startup's speed without cutting corners
Own the technical relationship with the founding team and investors on analog progress, reporting status in terms of risk retired, not tasks completed

What you will bring

Must-haves

7-10+ years of analog IC design with multiple shipped products and a record of first-silicon success on complex blocks
Demonstrated technical leadership: informal or formal, you have guided other designers' work to successful tapeouts
Strong program instincts: you can plan a multi-block tapeout, spot the critical path, and reallocate effort before slips become crises
Mastery of Cadence Virtuoso and Spectre, with the judgment to know when a simulation is trustworthy and when silicon will disagree
Clear, direct communication with founders, layout engineers, and customers; no surprises, no hidden risks
A coaching mindset: you develop designers through reviews and pairing rather than by redoing their work
B.S. or M.S. in Electrical Engineering; startup or small-team experience strongly preferred

Nice-to-haves

Experience standing up a new analog team, flow, or IP library from scratch
Familiarity with fundraising-adjacent technical storytelling: demos, benchmarks, and customer evaluations
Prior work in an IP licensing model where PPA numbers are the product