Junior ASIC Design Verification Engineer

ASIC Design Verification Engineer Entry-level (L3 equivalent) 0-2 years

Other levels: ASIC Design Verification Engineer Senior ASIC Design Verification Engineer Principal ASIC Design Verification Engineer Staff ASIC Design Verification Engineer Lead ASIC Design Verification Engineer

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The job description

Tech stack. SystemVerilog basics, UVM fundamentals, commercial simulators (VCS/Questa/Xcelium), waveform debug, Git, Python

About the role

You will start your verification career on the design verification team of a fabless semiconductor company, paired with senior engineers who will teach you how real chips get verified. You will contribute to block-level testbenches from your first month: writing checkers, building coverage, and debugging failures alongside the RTL designers who fix them. This is a mentored role with a clear growth path toward independent block ownership, and your progress will be measured, coached, and celebrated. You will learn the full close-the-loop cycle: finding a bug, documenting it clearly, and following it through to its RTL fix.

What you will achieve

Deliver working UVM components (monitors, checkers, coverage collectors) for assigned blocks, reviewed and merged into the team's testbenches within your first quarter.
Drive directed and constrained-random tests to expose real bugs, documenting each find with a clear reproduction and waveform evidence that designers can act on immediately.
Build functional coverage for your assigned features toward the team's closure targets, learning to read coverage reports, identify gaps, and target them with new tests.
Reduce your debug cycle time by mastering waveform analysis and log triage, resolving straightforward testbench failures independently within your first six months.
Ship at least one meaningful verification improvement per half (a new checker, a regression script, a coverage model) that your team adopts into its standard flow.

What you will bring

Must-haves

0 to 2 years of experience, including internships or strong academic projects in digital design verification.
Working knowledge of SystemVerilog and the fundamentals of UVM (agents, sequences, scoreboards, and the testbench build flow).
Understanding of digital logic: state machines, FIFOs, synchronous design, and basic protocols (AXI, APB, or similar).
Ability to read RTL and waveforms and to write clear bug reports with reproduction steps and supporting evidence.
Eagerness to learn from senior engineers and to take feedback on code quality and debug approach without defensiveness.
Reliable work habits: you show up prepared, ask questions early, and follow through on commitments.

Nice-to-haves

Academic or project experience with assertions (SVA) or formal tools.
Scripting experience in Python for test automation or data analysis.
Coursework or projects involving RISC-V, bus protocols, or FPGA prototyping.
Familiarity with Git and collaborative code review workflows.