Junior Analog IC Design Engineer

About the role

You will join a fabless semiconductor company as a junior analog IC design engineer, working inside a mixed-signal team with direct mentorship from senior designers. The team designs the analog building blocks inside the company's SoCs, and new graduates here grow fast because they own real circuits on real tapeouts. This role matters because the team's throughput depends on engineers who can take a well-defined block from schematic to verified layout: you will become that engineer within your first year.

What you will achieve

• Deliver your first production block to tapeout within 12 months, owning schematic design, simulation, and layout supervision with a senior mentor's guidance
• Build and run complete simulation testbenches covering corners, Monte Carlo, and mismatch, catching design weaknesses before they reach review
• Cut your own debug time by learning to read simulation failures structurally: bias, loading, and stability first, parameters second
• Present your blocks in design reviews and incorporate feedback cleanly, demonstrating measurable improvement in review outcomes tapeout over tapeout
• Support silicon bring-up of your blocks in the lab, correlating measured data against simulation and documenting what matched and what did not
• Grow into independent ownership of a second-generation block by the end of your second year, scoped with decreasing mentorship

What you will bring

Must-haves

• 0-2 years of experience, including strong graduate coursework or internships in analog IC design with a tapeout or MPW project
• Solid fundamentals: device physics, small-signal analysis, feedback, noise, and matching, demonstrated through coursework or project work
• Hands-on experience with Cadence Virtuoso schematic entry and Spectre simulation from university labs, internships, or prior roles
• Willingness to learn layout discipline: you will work closely with layout engineers and absorb matching and floorplan principles fast
• Clear technical writing and presentation skills for specs, review decks, and lab reports
• B.S. or M.S. in Electrical Engineering with an analog or mixed-signal focus; strong academic project portfolios welcome

Nice-to-haves

• A graduate thesis, publication, or conference paper in analog or mixed-signal circuits
• Familiarity with Verilog-AMS or SystemVerilog for basic behavioral modeling
• Any bench measurement experience from labs or internships: probing, characterization, or debug
• Exposure to Python or SKILL scripting for automating simulation setup and data analysis