IP Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, configurable testbenches, protocol compliance suites, AMBA VIP, formal property checking, IP-XACT or coreConsultant flows

About the role

You will verify reusable semiconductor IP at a company whose blocks ship into many different SoCs, which means your bugs multiply across every customer integration. You will partner with the IP designers to prove each configuration of the block, each protocol mode, and each corner the datasheet promises. Your verification is the product's guarantee: when it passes your signoff, integrators trust it sight unseen, and your release quality is the company's reputation.

What you will achieve

Deliver verification signoff for IP releases across all supported configurations, with a configuration coverage matrix proving every legal parameter combination was exercised.
Drive protocol compliance to 100 percent against the governing specification (AMBA, PCIe, USB, or equivalent), using certified VIP and directed compliance suites.
Ship IP releases with zero known bugs at each drop, measured by a release checklist covering coverage, CDC, lint, and formal proof status that you own.
Cut customer-reported issues by building integration-oriented tests (back-to-back, error injection, reset during traffic) that mimic real SoC usage, designed together with the IP designers.
Reduce release cycle time by automating the IP qualification flow so a new RTL drop reaches signoff-ready regression in under a week.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience, ideally with reusable or configurable IP blocks rather than single-instance designs.
Strong SystemVerilog/UVM skills with experience parameterizing testbenches across many configurations and proving the parameter space.
Deep knowledge of at least one industry-standard protocol and its compliance requirements, including how integrators misuse it.
Experience with formal verification applied to IP control logic and interface properties.
Understanding of what makes IP shippable: documentation, release notes, known-issue tracking, and backward compatibility across releases.
Ability to work closely with IP designers on microarchitecture trade-offs that affect verifiability and configurability.
Customer empathy: you verify the way an integrator will use the IP, including the ways they will use it wrong.

Nice-to-haves

Experience with safety or security certification requirements for IP (ISO 26262, Common Criteria).
Familiarity with IP packaging and delivery flows.
Knowledge of multiple protocol families (for example, AMBA plus a high-speed serial standard).
Exposure to customer support debug, turning field issues into verification improvements.