Instruction Set Architect (ISA)

CPU Architect Staff (L6 equivalent), scope across multiple teams 8-12 years

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The job description

Tech stack. ISA specification, Arm and RISC-V ISAs, formal ISA modeling, SystemVerilog, software toolchain awareness, Sail or ASL modeling, compatibility and compliance testing, architecture extension design

About the role

You will own the instruction set architecture at a semiconductor company, defining the contract between software and hardware that every program, compiler, and operating system depends on for decades. ISA architects make decisions with extraordinary longevity: instructions added today must be supported in silicon and software for generations, while mistakes become permanent compatibility burdens. You will design ISA extensions, write the formal specification, work with toolchain and software teams on enablement, and guard the architecture's coherence as it evolves.

What you will achieve

Design and specify new ISA extensions such as vector, matrix, cryptography, or virtualization features, proving their value with workload analysis and hardware cost modeling before committing the architecture to them.
Author and maintain the formal ISA specification, including precise instruction semantics, exception behavior, memory ordering rules, and system register definitions that hardware and software teams implement against.
Drive the hardware-software co-design process for new instructions, working with compiler, library, and OS teams so that extensions deliver real application speedups rather than unused opcode space.
Establish the ISA compliance and compatibility testing methodology, ensuring every implementation passes rigorous architectural conformance suites before it ships to customers.
Evaluate the long-term costs of ISA decisions including decoder complexity, verification burden, and software fragmentation, and steer the organization away from extensions whose lifetime cost exceeds their benefit.
Represent the company's ISA interests in industry bodies, partner engagements, or open-source ISA communities, building the ecosystem relationships that determine an ISA's success.

What you will bring

Must-haves

8 to 12 years of experience in ISA design, CPU architecture, or compiler and toolchain development with shipped products.
Deep understanding of at least one major ISA including its encoding, semantics, system architecture, and evolution history.
Experience writing formal architecture specifications with the precision that hardware implementation and software enablement demand.
Strong grasp of the hardware implementation costs of ISA features: decode complexity, datapath implications, and verification burden.
Working knowledge of compilers, assemblers, debuggers, and operating systems as consumers of the ISA contract.
Ability to reason about decades-long compatibility commitments and to say no to extensions that do not earn their permanent cost.
Excellent technical writing and cross-organizational influence skills, since ISA decisions affect every team in the company.

Nice-to-haves

Experience with formal ISA models in Sail, ASL, or similar frameworks.
Background in both RISC and vector or SIMD architecture design.
Participation in industry standards bodies or open ISA governance.