High-Speed Mixed Signal Designer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Cadence Virtuoso, SpectreRF, ADS, EMX, MATLAB, 28nm/16nm PDKs, high-speed lab equipment (BERT, sampling scopes)

About the role

You will design the high-speed analog front ends at a fabless semiconductor company building wireline and optical connectivity chips. The team lives above 10 GHz: broadband amplifiers, track-and-hold circuits, high-speed DACs and ADCs, and clock distribution that must stay clean at data rates where every picosecond matters. This role matters because link performance is set by your front end long before the DSP gets involved, and your jitter and bandwidth numbers define the product. You will work closely with packaging and signal-integrity engineers, since at these data rates the channel, the package, and your front end are one co-designed system.

What you will achieve

Ship broadband analog blocks (TIA, VGA, track-and-hold, or high-speed DAC) with measured bandwidth and linearity meeting spec at 25 Gbps and above on first silicon.
Drive clock distribution quality: design buffers and dividers that hold integrated jitter under the link budget (sub-100 fs RMS where required) across corners and supply variation.
Reduce ISI and channel-induced penalties by co-designing your front end with the equalization team, trading analog bandwidth against DSP complexity with measured data.
Own EM-accurate sign-off for your blocks: inductor and transmission-line modeling in EMX, package and bondwire co-simulation, and extracted-view bandwidth verification.
Cut lab debug time by building your own test plans and automation: BERT-based jitter tolerance, S-parameter verification, and eye-diagram analysis scripted in Python.

What you will bring

Must-haves

2-5 years designing high-speed analog circuits (broadband amplifiers, TIAs, VGAs, samplers, or high-speed data converters) in CMOS or BiCMOS.
Strong fundamentals in high-frequency design: s-parameters, transmission lines, matching networks, and bandwidth extension techniques (inductive peaking, fT doublers).
Fluency in SpectreRF for periodic steady-state analysis: PSS, PAC, PNOISE applied to real high-speed blocks.
Experience with EM modeling of on-chip passives and interconnect at 10 GHz and above.
Lab skills with high-speed instruments: sampling oscilloscopes, BERTs, VNAs, and the ability to correlate measurements to simulation.
At least one high-speed tapeout with lab-measured results you can discuss.

Nice-to-haves

Familiarity with PAM4 signaling and its linearity and SNR demands on the analog front end.
Knowledge of optical front-end design (photodiode interfaces, TIAs for optical links).
Experience with ESD structures that do not kill high-speed performance.