High-Speed Analog IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Multi-GHz signaling, CTLE, DFE, CDR, PAM4, jitter analysis, T-coils, ESD at speed, Cadence Virtuoso, Spectre, EM co-simulation

About the role

You will join a high-speed connectivity company designing the analog front ends behind multi-gigabit serial links. The team builds the receiver and transmitter circuits that push data across lossy channels at tens of gigabits per second. This role matters because every generation doubles the data rate while the channel gets worse: your equalization and clocking circuits decide whether the link closes. Data rates keep climbing while channel budgets stay flat, so circuit innovation is the only path forward. You will also run the equalization architecture trade studies that pick CTLE versus DFE versus FFE tap counts, balancing power against the link margin each customer channel demands.

What you will achieve

Ship transmitter and receiver front ends that close the link at target data rates with margin on the bathtub curve across worst-case channels
Design equalization chains (CTLE, FFE, DFE) that compensate channel loss with minimal power and area overhead
Deliver clock recovery circuits that hold lock across voltage, temperature, and supply noise while meeting jitter tolerance masks
Cut power per bit by optimizing bias, swing, and architecture choices against measured channel data rather than worst-case assumptions
Drive channel and package co-simulation with EM models, so lab measurements of insertion loss and crosstalk match simulation before tapeout
Support link bring-up in the lab with BERTs and oscilloscopes, debugging equalization adaptation and CDR behavior on real channels
Evaluate emerging signaling schemes and channel materials, prototyping what the next speed grade will require

What you will bring

Must-haves

2-5 years designing high-speed analog circuits with at least one shipped SerDes, PHY, or multi-GHz product
Strong understanding of jitter (random and deterministic), eye diagrams, and link-budget analysis for serial channels
Design experience with at least two of: CTLE, DFE, FFE, CDR, or high-speed output drivers
Proficiency in Cadence Virtuoso and Spectre for GHz-range design, including transient and periodic analyses
Working knowledge of transmission-line effects, s-parameters, and package/channel modeling at multi-GHz frequencies
Lab skills with high-bandwidth oscilloscopes, BERTs, and VNAs for link characterization and debug
B.S. or M.S. in Electrical Engineering with a high-speed or RF circuits emphasis

Nice-to-haves

PAM4 or higher-order modulation signaling experience
Familiarity with standards bodies and compliance testing (PCIe, Ethernet, USB)
Experience with adaptive equalization algorithms and digital calibration loops