High-Speed Analog Design Engineer

Analog Design Engineer Senior (L5 equivalent) 5-8 years

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Texas Instruments

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NXP

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The job description

Tech stack. High-speed analog design, SerDes front ends, CTLE and DFE equalization, Cadence Virtuoso, SpectreRF, channel modeling, jitter analysis, advanced CMOS nodes, PAM4 signaling

About the role

You will design high-speed analog front ends at a semiconductor company, building the transmitters, receivers, equalizers, and clocking circuits that move data at tens of gigabits per second. High-speed analog designers operate at the edge of what silicon can do: their circuits must overcome channel loss, crosstalk, jitter, and noise while consuming minimal power. You will design CTLEs, DFEs, VGAs, and phase interpolators, model channels rigorously, and prove your designs work across voltage, temperature, and process variation.

What you will achieve

Design high-speed receiver front ends including CTLE, VGA, and DFE tap structures that recover data reliably across lossy channels at multi-gigabit rates.
Design transmitter circuits including drivers, pre-emphasis, and serialization logic meeting stringent output swing, jitter, and return loss specifications.
Model channels and link budgets quantitatively, using S-parameters, statistical eye analysis, and time-domain simulation to prove margin before tapeout.
Design clocking circuits for high-speed links including phase interpolators, injection-locked oscillators, or CDR components with tight jitter requirements.
Optimize high-speed designs for power efficiency, since link power dominates IO budgets, without compromising bit error rate targets.
Validate high-speed circuits on silicon with BERT measurements, jitter decomposition, and eye diagram analysis, correlating measured margins against pre-silicon predictions to refine models for future designs.

What you will bring

Must-haves

5 to 8 years of experience in high-speed analog, SerDes, or wireline design with shipped products.
Deep understanding of channel impairments: loss, reflections, crosstalk, jitter sources, and their mitigation through equalization.
Strong circuit design skills for broadband amplifiers, comparators, and mixed-signal feedback loops at multi-GHz speeds.
Experience with link modeling including statistical simulation, channel S-parameters, and jitter budgeting.
Proficiency with advanced simulation techniques including SpectreRF, transient noise, and periodic steady state analysis.
Bench measurement expertise for high-speed signals including real-time scopes, BERTs, and phase noise analyzers.
Understanding of wireline standards such as PCIe, Ethernet, or USB and their electrical specifications.

Nice-to-haves

Experience with PAM4 signaling and its unique design challenges.
Knowledge of optical communication front ends or co-packaged optics.
Familiarity with ADC-based receivers and DSP-assisted equalization.
Background in advanced node design at 7nm or below.