Functional Verification Engineer

About the role

You will own feature-level verification at a fabless semiconductor company, working from the architecture specification outward to prove that every documented behavior of the design actually works. Functional verification is spec-driven: you translate feature descriptions into verification plans, coverage models, and test scenarios that leave no specified behavior unexercised. You will develop the habit of reading specifications adversarially, finding the ambiguities and contradictions before RTL gets written against them. Your measure of success is simple and unforgiving: no functional bug in your feature set reaches silicon undetected. The coverage models you build become the project's proof of completeness, and the scenario tests you write catch the feature-interaction bugs that random testing alone would miss.

What you will achieve

• Translate architecture specifications into verification plans that map every feature, including corner cases and error handling, to concrete coverage points.
• Achieve 100 percent functional coverage closure on assigned feature sets, with reviewed waivers for the small remainder that cannot be hit.
• Discover and file high-quality functional bugs at a rate that keeps the bug curve ahead of the RTL freeze schedule, with fewer than 10 percent invalid filings.
• Build scenario-based tests for complex feature interactions (for example, concurrent configuration changes during active data flow) that random testing alone misses.
• Reduce spec ambiguity escapes by flagging unclear or contradictory specification language during verification planning, before RTL is written against it.

What you will bring

Must-haves

• 2 to 5 years of functional verification experience on ASIC or complex FPGA designs.
• Demonstrated skill in writing verification plans directly from architecture and microarchitecture specifications.
• Strong functional coverage modeling: covergroups, crosses, and coverage-driven test refinement.
• Solid SystemVerilog and UVM skills for building the tests and checkers your plans require.
• SVA proficiency for capturing specified protocol and timing behavior as checkers.
• Analytical reading of specifications with a track record of finding spec bugs, not just RTL bugs.
• Disciplined bug reporting with clear expected-versus-actual behavior tied to spec sections.

Nice-to-haves

• Experience reviewing architecture specifications before RTL implementation begins.
• Familiarity with requirements-tracking tools linking features to verification results.
• Exposure to formal methods for verifying control-intensive features.
• Experience with model-based testing or requirements-driven verification tools.