Functional Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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Qualcomm

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Cadence

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The job description

Tech stack. SystemVerilog/UVM, functional coverage modeling, directed and constrained-random testing, scoreboarding, regression management

About the role

You will own functional correctness verification at a semiconductor company, the discipline of proving the design does what its specification promises across every feature and mode. Working in lockstep with designers and architects, you will translate specifications into verification plans, build the checkers that enforce them, and drive coverage to closure. When your functional signoff is complete, the features work as specified, and you can prove it feature by feature. You are the guardian of the specification's promises: every feature the datasheet claims must survive your verification, or it does not ship.

What you will achieve

Deliver verification plans traceable feature-by-feature to the design specification, with every requirement mapped to tests and coverage points in a living document.
Drive functional coverage to 100 percent of planned coverpoints across your blocks, with waivers documented and architect-approved, never hand-waved.
Ship self-checking scoreboards and protocol checkers that validate every transaction against the spec, catching functional bugs at their source before they propagate.
Cut specification ambiguity by raising clarification issues with architects and designers early, resolving them before RTL is written wherever possible.
Reduce regression escape risk by building directed tests for specification corner cases that random testing covers only by luck, prioritized by risk.

What you will bring

Must-haves

2 to 5 years of ASIC functional verification experience using SystemVerilog and UVM through coverage closure.
Proven skill in writing verification plans from specifications and tracking them to closure across milestones.
Strong functional coverage modeling: covergroups, coverpoints, crosses, and coverage-driven test planning that actually finds gaps.
Experience building transaction-level scoreboards and reference models for complex protocols or datapaths.
Sharp specification reading: you find the ambiguities and contradictions that become bugs if nobody asks.
Collaborative verification style: you work with designers to confirm intent before you call something a bug, but you do call it.
Tenacity for closure: the last 5 percent of coverage is where the real bugs hide, and you do not declare victory early.

Nice-to-haves

Experience with requirements management tools and traceability flows.
Familiarity with formal methods as a complement to functional coverage.
Knowledge of performance or interoperability testing beyond pure functionality.
Exposure to safety-critical verification with documentation and audit requirements.