FPGA Hardware Engineer

About the role

You will design the hardware platforms that FPGAs live on: power, clocks, configuration, and the high-speed interfaces that make programmable logic genuinely useful in products. FPGA hardware engineers own everything around the chip: the power delivery networks handling massive transient currents, the transceiver channels running at tens of gigabits per second, and the configuration schemes that get bitstreams loaded reliably every time. You will enable the logic designers to do their best work by giving them a platform that simply works, with clean power, stable clocks, and well-characterized channels. Your reward is a bring-up that goes smoothly because the board was right.

What you will achieve

• Design FPGA carrier boards with robust power delivery for high transient response, clean clocking networks, and validated high-speed transceiver channels
• Deliver reliable configuration schemes spanning flash-based, processor-driven, or network-loaded approaches, with fallback images and field-update support
• Validate transceiver performance through IBIS-AMI simulation and lab measurement, achieving target bit error rates on every lane with margin
• Debug board-level FPGA issues spanning power integrity, signal integrity, and configuration sequencing with systematic measurement-driven analysis
• Create platform documentation covering power sequencing, pin assignments, and constraints guidance that logic teams build on confidently

What you will bring

Must-haves

• 2 to 5 years designing hardware around FPGAs from Xilinx/AMD, Intel/Altera, Lattice, or Microchip with working shipped products
• Understanding of FPGA power requirements: core voltage transient behavior, power sequencing discipline, and decoupling strategies for large devices
• Experience with high-speed transceiver integration: reference clock quality, channel design, and link training validation in the lab
• Familiarity with FPGA configuration modes: JTAG, SPI flash, partial reconfiguration, and secure authenticated bitstream options
• Lab skills for FPGA board debug: JTAG chain debugging, power rail analysis under dynamic load, and transceiver eye diagram interpretation
• Knowledge of pin planning constraints: I/O standards, bank voltage rules, and clock-capable pin requirements for timing closure
• BS in Electrical Engineering or equivalent experience

Nice-to-haves

• Basic HDL knowledge in Verilog or VHDL enabling effective technical collaboration with logic designers
• Experience with SoC FPGAs such as Zynq or Stratix 10 SoC including processor subsystem integration
• Familiarity with high-speed memory interfaces to FPGAs: DDR4, HBM, or QDR implementations
• Experience with PCIe endpoint integration on FPGA platforms including configuration and link training