Formal Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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NVIDIA

Qualcomm

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Broadcom

Marvell

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The job description

Tech stack. SystemVerilog Assertions (SVA), Cadence Jasper, Synopsys VC Formal, model checking, equivalence checking, connectivity apps, Python

About the role

You will prove correctness mathematically at a fabless semiconductor company, using formal verification to exhaustively check the properties that simulation can only sample. This role owns property checking for control-intensive logic: arbiters, state machines, bus fabrics, and clock-domain crossings where a single missed corner case becomes a silicon bug. Your proofs either come back clean or produce counterexamples that no amount of random testing would have found, and both outcomes make the chip better. You will build the property libraries and proof strategies that scale formal across the project, teach simulation-focused engineers to write provable assertions, and drive the convergence techniques that close proofs on realistically complex designs. In the blocks you own, correctness is not a statistical argument; it is a proof.

What you will achieve

Prove full unbounded correctness on assigned control-logic blocks, closing all properties with no bounded-only waivers at signoff.
Find at least five high-severity bugs per project through formal counterexamples that simulation regressions missed.
Build reusable SVA property libraries for common structures (arbiters, FIFOs, one-hot state machines) adopted across multiple blocks.
Drive proof convergence on complex designs, using abstraction, case-splitting, and assume-guarantee techniques to close proofs within compute budgets, and document the abstraction strategy so proofs remain reproducible across RTL revisions.
Deliver CDC and connectivity signoff using formal apps, covering every clock-domain crossing and top-level connection in the assigned scope.

What you will bring

Must-haves

2 to 5 years of formal verification experience with Jasper, VC Formal, or equivalent model-checking tools.
Expert-level SVA: writing properties, sequences, and assumptions that are both correct and provable.
Deep understanding of model-checking fundamentals: state-space explosion, bounded versus unbounded proofs, and abstraction techniques.
Experience with formal apps for connectivity checking, CDC verification, and X-propagation analysis.
Ability to debug counterexamples and distinguish genuine RTL bugs from over-constrained properties.
Familiarity with equivalence checking flows (LEC/Formality) for RTL-to-netlist verification.
Scripting skills for automating formal runs, proof management, and results tracking.

Nice-to-haves

Experience with sequential equivalence checking or datapath formal techniques.
Knowledge of security property verification for hardware trust concerns.
Exposure to combining formal results with simulation coverage for hybrid signoff.
Programming skills for building custom formal apps or proof automation.