Formal Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. Jasper (Cadence), VC Formal (Synopsys), SVA property development, formal apps (CDC, X-prop, connectivity), proof convergence techniques

About the role

You will prove correctness mathematically at a semiconductor company that uses formal verification to eliminate entire classes of bugs before simulation ever runs. Partnering with RTL designers, you will write properties that capture design intent, drive proofs to convergence, and find the deep corner-case bugs that random testing statistically never reaches. Where simulation samples behavior, your work guarantees it, and your counterexamples have the authority of proof. Your bug reports are the most persuasive documents in the program, because a failed proof leaves no room for debate about whether the bug is real.

What you will achieve

Deliver proven property sets for control-intensive blocks (arbiters, FIFOs, bus fabrics, power controllers) with full proof convergence before each tapeout.
Drive formal-first verification on at least two blocks per program, catching deep bugs (deadlock, starvation, illegal states) that simulation missed entirely.
Ship reusable formal app deployments (connectivity, CSR, X-propagation checks) across the design, running clean on every RTL drop as part of the standard flow.
Cut proof runtime by mastering abstraction, assume-guarantee partitioning, and helper assertions, keeping full proof suites within overnight runtimes.
Reduce designer friction by embedding with RTL teams: reviewing properties with designers and turning counterexamples into RTL fixes within days, not weeks.

What you will bring

Must-haves

2 to 5 years of ASIC verification or design experience with hands-on formal verification work through proof convergence.
Strong SVA skills: writing correct, complete properties and understanding vacuity, fairness, and proof semantics.
Experience with at least one commercial formal tool (Jasper, VC Formal, or Questa Formal) including its apps and proof management.
Understanding of the techniques that make proofs converge: black-boxing, case splitting, lemmas, and constraint development.
Solid digital design fundamentals: you read RTL and microarchitecture with the precision formal work demands.
Persistence for the hardest debug: analyzing counterexamples to distinguish real bugs from over-constraining, without crying wolf.
Communication skills to make formal results legible to designers who do not live in the formal world.

Nice-to-haves

Experience with sequential equivalence checking or datapath formal techniques.
Familiarity with formal coverage metrics (proof core, cone-of-influence analysis).
Knowledge of security property verification or safety-critical formal flows.
Exposure to combining formal with simulation in a unified signoff story.