Execution Unit CPU Designer

About the role

You will design CPU execution units at a semiconductor company, implementing the integer ALUs, address generation units, and specialized functional units where instructions actually execute. Execution unit designers own the logic that determines the processor's raw throughput: their units must deliver results every single cycle at aggressive frequencies while handling every data type, exception condition, and corner case correctly. Your designs sit on the most timing-critical paths in the core, and your skill directly bounds the processor's performance.

What you will achieve

• Design execution units including integer ALUs, address generation units, branch units, and specialized functional units, meeting aggressive cycle-time targets through skilled circuit-aware RTL design.
• Implement operand delivery, bypass, and forwarding networks that minimize effective latency between dependent instructions, coordinating closely with pipeline architects on timing budget allocation.
• Handle all exception and corner-case behavior correctly including arithmetic overflow, division edge cases, and precise exception signaling within out-of-order execution contexts.
• Optimize execution units for power and area alongside timing, making quantitative tradeoffs between parallel and serial implementations where the performance requirements allow flexibility.
• Verify execution functionality exhaustively with directed tests for corner cases, constrained-random testing for unexpected interactions, and formal methods for critical properties.
• Support timing closure, physical implementation, and silicon debug for your units, applying deep knowledge of the implementation to resolve issues quickly and correctly.

What you will bring

Must-haves

• 5 to 8 years of experience in execution unit, datapath, or high-performance logic design with shipped silicon.
• Deep knowledge of computer arithmetic and its efficient hardware implementation across a range of structures.
• Expert timing intuition with a proven ability to close aggressive cycle times on complex logic.
• Strong SystemVerilog design skills for intricate, timing-critical control and datapath logic.
• Thorough verification discipline for arithmetic correctness including every edge case and exception scenario.
• Understanding of pipeline integration: how execution units interact with instruction scheduling, bypass networks, and writeback.
• Persistence and creativity in optimizing critical paths without ever compromising correctness or robustness.

Nice-to-haves

• Experience with specialized functional units such as cryptographic accelerators, CRC engines, or bit manipulation units.
• Knowledge of approximate computing techniques and their applicability to error-tolerant workloads.
• Familiarity with custom datapath design flows or standard-cell optimization.
• Exposure to out-of-order scheduler design and wakeup-select timing challenges.