Etch/Deposition Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. plasma etch, ALD, CVD, PVD, endpoint detection, chamber conditioning, selectivity control, profile metrology, OES

About the role

A wafer fab needs an etch and deposition engineer to own thin-film formation and pattern transfer processes, the steps that physically build the transistors and interconnects. You will develop plasma etch and deposition recipes that hit profile, selectivity, and uniformity targets across every wafer, and you will sustain them through chamber aging, PMs, and hardware changes. Your processes define the physical structures every device depends on, so profile control and film quality are never just specifications, they are the product. The engineer also owns the chamber-matching program that keeps etch and deposition tools interchangeable, so production can flex across the fleet without requalification.

What you will achieve

Deliver etch and deposition recipes with within-wafer uniformity below 2 percent one sigma on critical films, verified by routine monitoring across all chambers in the fleet, with SPC limits reviewed quarterly and updated after process changes.
Reduce etch-induced profile defects such as bowing, notching, or micro-trenching by 30 percent through chamber seasoning control, endpoint optimization, and gas-distribution tuning across the showerhead for edge-to-center uniformity control.
Drive selectivity improvements that widen process windows for high-aspect-ratio structures, giving integration the margin it needs for aggressive designs and next-node shrinks.
Own film stress and composition control, keeping parameters inside spec across 500 consecutive lots with no drift-driven excursions, verified by routine film metrology.
Cut recipe development time by 25 percent using DOE-driven recipe screening instead of one-factor-at-a-time tuning, reaching qualified recipes with fewer test wafers and less engineering time per qualification.

What you will bring

Must-haves

BS or MS in chemical engineering, materials science, physics, or electrical engineering.
2 to 5 years working with plasma etch, CVD, PVD, or ALD tools in a fab environment with recipe ownership.
Understanding of plasma physics fundamentals including ion energy, radical density, and chamber pressure effects on etch and deposition behavior.
Experience with endpoint detection and optical emission spectroscopy for process control and fault detection.
Hands-on DOE and statistical analysis for process development, with recipes qualified through designed experiments.
Familiarity with cross-section SEM and profile metrology interpretation for etch profile validation.

Nice-to-haves

ALD process development experience for conformal films in 3D structures.
Experience with high-aspect-ratio etch for 3D NAND or DRAM applications.
Knowledge of atomic layer etching techniques and their process control requirements.