Emulation Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Palladium, Zebu, emulation bring-up, transaction-level modeling, HW/SW co-verification, SystemVerilog, SCE-MI, Python

About the role

You will own emulation-based verification at a fabless semiconductor company, running the full SoC on Palladium or Zebu platforms at speeds simulation can never reach. Emulation verification bridges pre-silicon and software: booting operating systems, running application workloads, and validating hardware-software interactions months before silicon. Your emulation environment is where firmware teams do their bring-up and where system-level bugs get caught while RTL can still change cheaply. You will master the compile flows, transactors, and debug techniques that make emulation productive, and you will keep the platform stable and fast for every team that depends on it. When software boots on first silicon without surprises, your emulation already proved it would.

What you will achieve

Bring up the full SoC design on the emulation platform, reaching OS boot within four weeks of RTL handoff.
Build transaction-level testbenches and SCE-MI bridges that accelerate simulation testcases by 100x or more on the emulator.
Enable firmware and software teams with a stable emulation environment maintaining 90 percent or better platform availability during bring-up.
Find system-level bugs (boot failures, driver issues, performance pathologies) in emulation that simulation regressions missed, at a rate of at least ten per project.
Optimize emulation throughput through compile-time partitioning and runtime techniques, cutting workload execution time by 40 percent, and document the partitioning strategy so future SoC revisions compile cleanly on the first attempt.

What you will bring

Must-haves

2 to 5 years of emulation experience with Palladium, Zebu, or Veloce on complex SoC designs.
Strong SystemVerilog skills including synthesizable testbench constructs and transactors for emulation.
Experience with emulation compile flows: partitioning, synthesis for emulation, and debug instrumentation.
Understanding of HW/SW co-verification: running firmware and software stacks on emulated hardware.
Familiarity with SCE-MI or similar transaction-level interfaces between testbench and DUT.
Debug skills for emulation-specific issues: clocking, reset, and timing artifacts of the emulation environment.
Scripting ability for automating emulation runs, results collection, and platform monitoring.

Nice-to-haves

Experience with hybrid emulation combining virtual platforms and RTL.
Knowledge of performance analysis and profiling on emulation platforms.
Exposure to post-silicon validation to correlate emulation findings with silicon behavior.
Experience with in-circuit emulation using real hardware interfaces.