Emulation and Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. Cadence Palladium, Synopsys Zebu, emulation compile flows, SystemVerilog/UVM, SCE-MI transactors, in-circuit emulation, hybrid emulation

About the role

You will run design verification on hardware emulation platforms at a semiconductor company building chips too large to verify by simulation alone. You will compile multi-million-gate designs onto Palladium or Zebu systems, build transactor-based test environments, and execute the long software-driven scenarios that find system-level bugs months before silicon. You bridge two worlds: RTL designers who need fast, deep debug and software teams who need a working chip months early, and both depend on your platform staying productive.

What you will achieve

Deliver emulation builds of the full design or major subsystems with compile turnaround under 48 hours, keeping the platform productive across RTL drops.
Drive emulation regression suites (boot, OS bring-up, long stress scenarios) to stable, repeatable pass rates, triaging failures to RTL, model, or environment causes within a day.
Ship transactor-based verification environments that run real firmware and driver code against the DUT at megahertz speeds, covering scenarios simulation cannot reach in reasonable time.
Cut time-to-first-bug by establishing debug flows (waveform capture, signal forcing, checkpoint and restore) that let designers debug emulation failures as efficiently as simulation failures.
Reduce program risk by partnering with RTL designers on emulation-specific design requirements (clocking, asynchronous interfaces, memory modeling) early in the design phase, before they become compile blockers.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with hands-on use of at least one emulation platform (Palladium, Zebu, or Veloce).
Strong SystemVerilog skills and working knowledge of UVM, adapted to emulation-friendly coding styles that compile and run efficiently.
Understanding of emulation compile flows: partitioning, synthesis for emulation, clock handling, and resource utilization trade-offs.
Experience with transactors or SCE-MI interfaces connecting testbenches to the emulated DUT.
Debug skills spanning RTL waveforms and software-driven scenarios, with the patience for long, complex failure analysis.
Collaborative approach with both hardware designers and embedded software engineers, translating between their needs.
Operational discipline: you manage compile queues, platform scheduling, and environment versioning so the team is never blocked.

Nice-to-haves

Experience with hybrid emulation (virtual platforms coupled to RTL) or in-circuit emulation with real peripherals.
Familiarity with power estimation or performance analysis on emulation.
Knowledge of emulation capacity planning and multi-user scheduling.
Exposure to post-silicon or software bring-up flows that reuse emulation infrastructure.