CPU Verification Architect

About the role

You will define the verification strategy for CPU development at a semiconductor company, architecting the methodology that proves the processor is correct before it tapes out. Verification architects design the testbench architecture, the coverage model, the formal verification plan, and the bug triage process for some of the most complex logic ever built. A single escaped CPU bug can cost tens of millions of dollars, so this role carries enormous responsibility and demands exceptional rigor, creativity in finding corner cases, and deep architectural understanding.

What you will achieve

• Define the complete verification strategy for a CPU program including simulation-based, formal, and emulation-based approaches, with clear coverage goals and sign-off criteria for each milestone.
• Architect the testbench and verification IP for the CPU or major subsystems, ensuring reusability across the program and adaptability as the microarchitecture evolves.
• Design the functional coverage model that measures verification completeness, tying coverage points to the architecture specification so that coverage genuinely reflects verified behavior.
• Lead the formal verification effort for critical control logic, protocols, and tricky corner cases, proving correctness properties that simulation alone cannot guarantee.
• Establish the bug triage, root cause analysis, and fix verification processes that keep the program moving quickly without letting quality slip under schedule pressure.
• Drive verification sign-off at tapeout with honest, data-backed assessments of residual risk, ensuring leadership understands exactly what has and has not been proven.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU or complex ASIC verification with at least one full tapeout cycle.
• Deep understanding of modern verification methodologies including UVM, constrained random stimulus, coverage-driven verification, and formal methods.
• Strong architectural knowledge of processors, enabling you to anticipate where bugs hide and which corner cases matter.
• Experience designing verification environments and coverage models for complex, concurrent hardware.
• Fluency in SystemVerilog and familiarity with assertion-based verification.
• Analytical rigor and professional skepticism: you assume bugs exist until proven otherwise and you design the proof.
• Clear communication skills for reporting verification status and risk honestly to program leadership.

Nice-to-haves

• Experience with emulation or FPGA prototyping for pre-silicon software and system validation.
• Knowledge of ISA-level compliance testing and architectural conformance suites.
• Background in post-silicon validation and debug methodologies.