CPU Microarchitecture Design Engineer

About the role

You will work at the boundary between architecture and implementation at a semiconductor company, translating architectural intent into implementable microarchitecture for CPU blocks. Microarchitecture design engineers define the pipeline structures, control logic, and interface protocols that RTL designers build from, working at a level of detail where every queue depth, arbitration policy, and timing assumption matters enormously. You will model your structures quantitatively, specify them with precision, prototype the riskiest pieces in RTL, and guide implementation through tapeout and silicon validation.

What you will achieve

• Define detailed microarchitectures for CPU blocks including pipeline organization, queue sizing, arbitration schemes, and control protocols, validated through modeling and analysis before RTL design begins.
• Produce microarchitecture specifications complete enough that RTL designers can implement without architectural ambiguity, covering every state, transition, interface protocol, reset behavior, and corner case.
• Prototype timing-critical or high-risk structures in RTL to validate feasibility early, retiring implementation risk before the broader design effort commits significant resources.
• Drive PPA optimization at the microarchitecture level, making the structural decisions on pipeline depth, parallelism, and resource sizing that determine whether the block meets its frequency, power, and area targets.
• Partner with architects on feasibility assessment of proposed features and with RTL designers on faithful implementation, serving as the essential bridge between the two disciplines.
• Support verification and silicon debug for your blocks, applying your deep structural knowledge to diagnose the subtlest functional and performance issues that others cannot explain.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU microarchitecture, high-performance RTL design, or performance modeling with shipped silicon.
• Deep understanding of pipelining, speculation and recovery, out-of-order execution, memory subsystem microarchitecture, and their interactions.
• Strong quantitative skills for sizing structures and evaluating tradeoffs through modeling, analysis, and first-principles reasoning.
• SystemVerilog fluency sufficient to prototype microarchitectural ideas quickly and to review implementation RTL with a critical eye.
• Understanding of timing closure realities and physical design implications of microarchitectural choices.
• Precise technical writing for specifications that implementation teams depend on daily.
• The judgment to balance architectural ambition against implementation risk, schedule pressure, and verification cost, and to explain those balances convincingly.

Nice-to-haves

• Experience with formal methods for validating microarchitectural protocols.
• Knowledge of low-power microarchitecture techniques such as fine-grained clock gating.
• Background spanning both architecture modeling and hands-on RTL implementation.
• Familiarity with queueing theory or applied probability for structural sizing.