CPU Memory Subsystem Architect

About the role

You will architect the memory subsystem of a CPU at a semiconductor company, designing the caches, prefetchers, interconnects, and memory controllers that feed the execution engine. Memory subsystem architects work on the part of the processor where many programs actually win or lose: data must arrive on time, coherency must be correct under every race, and bandwidth must scale with core count. You will define cache hierarchies, coherency schemes, prefetching strategies, and quality-of-service policies, then prove them in models and specifications.

What you will achieve

• Define the cache hierarchy for a CPU program including sizes, associativities, latencies, inclusivity policies, and partitioning schemes, optimized through modeling across the target workload set.
• Architect the coherency protocol and its interaction with the memory ordering model, producing specifications precise enough for correct implementation and formal verification.
• Design prefetching and memory-level parallelism strategies that measurably reduce effective memory latency on real workloads without blowing the power budget.
• Model memory subsystem performance under multi-core and multi-threaded contention, defining quality-of-service and bandwidth allocation policies that protect latency-sensitive workloads.
• Partner with SoC and system architects on the memory controller interface, interconnect topology, and address map, ensuring the CPU memory subsystem integrates cleanly at the system level.
• Validate the shipped memory subsystem against performance and correctness targets using post-silicon measurements and directed stress testing.

What you will bring

Must-haves

• 5 to 8 years of experience in cache or memory subsystem architecture, design, or performance modeling with shipped products.
• Deep understanding of cache hierarchies, coherency protocols such as MESI and MOESI variants, memory consistency models, and their hardware implications.
• Experience modeling memory subsystem performance and using models to drive sizing and policy decisions.
• Knowledge of DRAM characteristics, memory controller scheduling, and interconnect topologies and how they constrain CPU-side design.
• Fluency in at least one major ISA's memory model and its consequences for hardware and software.
• Ability to write precise specifications for complex concurrent protocols that implementation and verification teams can execute against.
• Strong debugging instincts for the subtle races and corner cases that define memory subsystem correctness.

Nice-to-haves

• Experience with multi-socket or chiplet-based coherency domains.
• Familiarity with persistent memory, CXL-attached memory, or other emerging memory technologies.
• Knowledge of formal methods applied to coherency verification.