CPU Logic Design Engineer

About the role

You will design processor logic at a semiconductor company, implementing the datapath and control structures that make up the CPU's functional blocks. Logic design engineers focus on getting the gates right: correct functionality, clean timing, reasonable power, and compact area, delivered through disciplined RTL design and thorough verification. You will own blocks from specification through integration, developing the craftsmanship and the systematic debug skills that distinguish reliable designers from merely productive ones.

What you will achieve

• Implement CPU logic blocks in SystemVerilog from microarchitecture specifications, delivering functionally correct RTL that meets timing, power, and area targets on the program schedule.
• Develop block-level testbenches and verification plans, driving functional and code coverage to the targets required for confident integration into the larger design.
• Debug complex functional failures systematically, using waveforms, assertions, and analytical reasoning to reach root causes efficiently rather than guessing.
• Close timing on your blocks through skilled RTL structuring, pipeline balancing, and close collaboration with physical design engineers on critical paths.
• Maintain clean lint, CDC, RDC, and design-rule status on your blocks throughout the program, resolving violations promptly as part of normal design work rather than in a pre-tapeout scramble.
• Support integration and system-level verification, resolving issues in your blocks quickly, communicating status clearly, and helping neighboring teams with interface questions.

What you will bring

Must-haves

• 2 to 5 years of experience in digital logic design for processors, SoCs, or complex ASICs with tapeout exposure.
• Strong synthesizable SystemVerilog skills with attention to coding style, readability, and long-term maintainability.
• Good understanding of synchronous design principles: clocking, resets, FIFOs, arbiters, synchronizers, and state machine design.
• Experience with simulation-based verification and a systematic, evidence-driven debug methodology.
• Familiarity with synthesis flows, timing constraints, and static timing analysis concepts.
• Scripting skills in Python or TCL for design automation and regression management.
• Craftsmanship mentality: you take pride in clean, correct, well-documented logic that others can build on.

Nice-to-haves

• Exposure to low-power design techniques including clock gating and power intent specification.
• Knowledge of CPU pipelines or specific functional units such as ALUs, shifters, or multipliers.
• Experience with assertion-based verification and formal property checking basics.
• Familiarity with emulation or FPGA prototyping for design validation.