CPU Front-End Design Engineer

About the role

You will design the front-end of CPU pipelines at a semiconductor company, implementing the instruction fetch, branch prediction interfaces, and decode logic that keep the execution engine supplied with work. Front-end designers own the part of the processor that determines whether expensive execution resources stay productive: their fetch pipelines must deliver high bandwidth, their redirect handling must be fast, and their decode must be correct, all at aggressive cycle times. A starved backend wastes the entire core, so front-end quality directly bounds the processor's achievable performance.

What you will achieve

• Design instruction fetch pipelines including next-PC generation, branch target buffer interfaces, predictor update paths, instruction cache access, and predecode logic, meeting aggressive cycle-time targets.
• Implement branch prediction interfaces and mispredict redirect handling with minimal penalty cycles, working closely with prediction architects on the timing-critical paths that define redirect latency.
• Design decode and micro-op expansion logic handling the complete ISA including complex, multi-micro-op instructions, with correct behavior for faults, exceptions, and microcode assists.
• Optimize front-end structures for power efficiency since fetch and decode logic is active nearly every cycle, applying clock gating and activity-aware techniques without compromising fetch bandwidth.
• Verify front-end functionality rigorously including the subtle interactions of speculation, redirects, pipeline flushes, and exception prioritization that define correct behavior.
• Support performance tuning and debug of the front-end on silicon, analyzing fetch efficiency, redirect costs, and decode bottlenecks to guide current fixes and future microarchitectures.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU front-end, fetch and decode, pipeline, or high-performance control logic design with shipped silicon.
• Deep understanding of branch prediction algorithms, predictor structures, and their hardware implementation tradeoffs.
• Strong SystemVerilog design skills for timing-critical control and datapath logic with complex state interactions.
• Knowledge of instruction fetch microarchitecture: taken-branch bandwidth challenges, cache latency hiding, predecode, and queueing between fetch and decode.
• Timing closure experience on aggressive cycle-time targets with realistic physical design collaboration.
• Verification discipline for speculative logic with intricate recovery, redirect, and exception behavior.
• Clear understanding of how front-end performance including fetch bandwidth and mispredict penalty translates into overall IPC.

Nice-to-haves

• Experience with advanced fetch techniques such as trace caches, decoupled front-ends, or streaming fetch buffers.
• Familiarity with variable-length ISA decode complexity tradeoffs and predecode strategies.
• Knowledge of security implications of speculative front-end behavior including transient execution mitigations.
• Exposure to fetch-directed prefetching or other front-end-driven memory system optimizations.