CPU Architect

About the role

You will join a semiconductor company defining its next generation of high-performance processors, working on the architecture team that decides what the chip will be long before a single line of RTL is written. This team carries the responsibility of balancing performance, power, and area against product goals and market realities, turning competitive analysis and workload insights into a concrete microarchitecture that hundreds of engineers will implement over multiple years. In this role you will own well-defined pieces of the microarchitecture definition, prove your ideas rigorously in cycle-accurate performance models, and carry them through detailed specification, implementation support, and post-silicon correlation.

What you will achieve

• Define the microarchitecture for one or more core subsystems such as instruction fetch, decode, out-of-order execution, or the memory pipeline on a new CPU program, targeting a double-digit IPC uplift over the prior generation while respecting strict power and area budgets.
• Build and calibrate cycle-accurate performance models that predict final silicon performance within 5 percent on key customer workloads, giving the program a trustworthy projection early enough to guide major investment decisions.
• Drive performance, power, and area tradeoff decisions with quantitative data and clear analysis, presenting well-reasoned options and a defensible recommendation to senior architects and product leadership at every major program milestone.
• Author complete architecture specifications that the RTL design team can implement without ambiguity, including precise interface definitions, reset and initialization behavior, error handling, and exhaustive corner-case descriptions.
• Partner closely with design, verification, and physical design teams from specification through tapeout, resolving microarchitecture issues uncovered during implementation while protecting the program's performance commitments.
• Characterize competitive processors and emerging workloads such as AI inference and cloud-native applications in depth, so the architecture roadmap stays grounded in where the market is heading rather than where it has been.

What you will bring

Must-haves

• 2 to 5 years of experience in CPU microarchitecture, performance modeling, or CPU RTL design with exposure to real product development.
• Strong understanding of modern out-of-order processor pipelines including branch prediction, register renaming, instruction scheduling, memory disambiguation, and precise exception handling.
• Hands-on experience building, calibrating, and extending an architectural simulator such as gem5 or SST for design exploration.
• Familiarity with at least one major ISA (Arm, RISC-V, or x86) and a clear understanding of its implications for hardware complexity and software ecosystems.
• Ability to read and write SystemVerilog fluently enough to collaborate closely with design engineers on implementation tradeoffs and feasibility.
• Clear technical writing skills for producing architecture specifications that large, distributed teams can execute against without constant clarification.
• Analytical discipline and intellectual honesty: you form hypotheses, test them rigorously in models, and let the data decide even when it contradicts your intuition.

Nice-to-haves

• Experience with workload analysis using SPEC, Geekbench, datacenter fleet traces, or mobile application profiles.
• Exposure to power modeling methodologies or physical design constraints and how they shape architectural choices.
• Contributions to open-source ISA efforts, processor projects, or architectural simulators.
• Familiarity with the security implications of microarchitectural choices including side-channel considerations.