Core CPU Design Engineer

About the role

You will design the CPU core pipeline at a semiconductor company, implementing the fetch, decode, rename, dispatch, issue, execute, and retire stages that form the heart of the processor. Core designers own the most performance-critical logic in the chip: their pipelines must sustain high instructions-per-cycle at aggressive frequencies while meeting power and area budgets. You will implement intricate control and datapath logic, close the toughest timing paths in the design, verify deeply concurrent behavior, and see your pipeline execute real software on real silicon.

What you will achieve

• Design and implement core pipeline stages including instruction fetch, decode, rename, dispatch, issue, execute, and commit logic, meeting aggressive frequency and IPC targets simultaneously.
• Implement out-of-order execution structures such as reservation stations, reorder buffers, physical register files, and load-store queues with correct handling of speculation, recovery, and precise exceptions.
• Close timing on the core's most critical paths through skilled RTL design, pipeline stage balancing, and close collaboration with physical design on placement, routing, and repeater planning.
• Drive verification of core functionality to the quality required for first-silicon success, with particular attention to the corner cases of speculation, exception handling, and memory ordering.
• Optimize the core implementation for power and area without compromising frequency and IPC targets, making principled tradeoffs backed by quantitative data.
• Support silicon bring-up, debug, and performance validation of the core, applying deep implementation knowledge to diagnose and resolve the most challenging functional and performance issues.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU core, high-performance pipeline, or out-of-order logic design with shipped silicon.
• Deep understanding of out-of-order execution, branch prediction interfaces, speculation and recovery mechanisms, and precise exception handling.
• Expert SystemVerilog design skills with a track record on timing-critical, functionally intricate processor logic.
• Strong verification skills for complex concurrent control logic with subtle corner cases that only deep understanding reveals.
• Proven timing closure ability on aggressive frequency targets with realistic physical design collaboration.
• Fluency in at least one major ISA and its implications for core implementation choices.
• Resilience and systematic thinking for debugging the hardest problems in the design, sustained over long, difficult debug efforts.

Nice-to-haves

• Experience across multiple core generations or microarchitectures for comparative perspective.
• Knowledge of advanced speculation techniques and their implementation costs and risks.
• Familiarity with performance counter, trace, and debug infrastructure design.
• Exposure to security considerations in speculative processor design.