Core Architect

About the role

You will own the architecture of a CPU core at a semiconductor company, defining the pipeline, execution resources, and control structures that determine its performance and efficiency. The core architect is responsible for the heart of the processor: every instruction flows through the structures you define, and your decisions on width, depth, speculation, and resource sizing set the ceiling for what the product can achieve. You will model aggressively, specify precisely, and defend your architecture with data through every program milestone.

What you will achieve

• Define the complete microarchitecture of a CPU core including fetch, decode, rename, dispatch, issue, execute, and retire, targeting the program's IPC, frequency, power, and area goals simultaneously.
• Deliver a calibrated performance model of the core that projects final silicon performance within 3 percent, giving the program confidence to commit major resources to implementation.
• Make the defining pipeline tradeoff decisions of the program, such as pipeline depth versus frequency, issue width versus power, and speculation aggressiveness versus mispredict cost, each backed by thorough modeling.
• Author the core architecture specification that the design team implements, covering every pipeline stage, interface, control signal, reset behavior, and corner case with precision.
• Guide the core through implementation, verification, and physical design, resolving the inevitable conflicts between the ideal architecture and implementation realities while protecting performance commitments.
• Validate the shipped core against its performance targets using silicon measurements, and document the lessons that will make the next core better.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU core architecture, performance modeling, or high-performance core RTL design with shipped silicon.
• Deep knowledge of out-of-order pipeline design including branch prediction, fetch bandwidth, rename, scheduling, execution clusters, and memory ordering.
• Track record of owning significant core subsystems or full cores through at least one tapeout.
• Strong modeling and analysis skills with the discipline to calibrate against reality and quantify uncertainty.
• Fluency in at least one major ISA and understanding of its software ecosystem implications.
• Ability to write architecture specifications that large design teams implement without ambiguity.
• The judgment to balance competing demands of performance, power, area, timing, and schedule, and to explain those balances convincingly.

Nice-to-haves

• Experience across multiple core generations or market segments such as client, server, and mobile.
• Knowledge of advanced techniques such as value prediction, runahead execution, or helper-thread architectures.
• Familiarity with the physical design implications of core floorplanning and pipeline layout.