CMOS Analog Design Engineer

Analog Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. CMOS analog design, Cadence Virtuoso, Spectre simulation, amplifiers and references, switched-capacitor circuits, Monte Carlo analysis, layout supervision, Python, low-voltage design techniques

About the role

You will design CMOS analog circuits at a semiconductor company, working with the mainstream process technology behind the vast majority of integrated circuits, from mobile SoCs to automotive controllers. CMOS analog designers master the art of achieving precision, speed, and efficiency using standard digital CMOS processes, navigating the tradeoffs of low supply voltages, limited intrinsic gain, and significant device mismatch. You will design amplifiers, references, filters, and switched-capacitor circuits, taking them from specification through layout to validated silicon.

What you will achieve

Design CMOS analog blocks including two-stage and folded-cascode op-amps, comparators, bandgap references, and continuous-time filters meeting gain, bandwidth, noise, and power specifications.
Design switched-capacitor circuits including sample-and-holds, integrators, and programmable gain stages with careful attention to charge injection, clock feedthrough, and kT/C noise, verified through transient noise simulation.
Simulate designs across PVT corners and Monte Carlo mismatch, ensuring robust performance and acceptable parametric yield before committing to tapeout, with margin for high-volume manufacturing.
Navigate low-voltage design constraints creatively, using techniques such as bulk-driven inputs, switched op-amps, or inverter-based amplifiers where headroom is limited, and verifying robustness across corners.
Supervise layout with rigorous attention to matching, common-centroid structures, dummy devices, and parasitic control, verifying post-layout performance through extraction and iterating where parasitics degrade specifications.
Validate your circuits on silicon through bench measurements, correlating results with simulation and refining models and practices based on findings.

What you will bring

Must-haves

2 to 5 years of experience in CMOS analog IC design with silicon validation results.
Strong analog fundamentals: device physics, small-signal analysis, feedback, noise, and mismatch statistics.
Proficiency with Cadence Virtuoso and Spectre including corner, Monte Carlo, and post-layout simulation flows.
Experience with switched-capacitor circuit design and its non-idealities.
Understanding of low-voltage analog design challenges and mitigation techniques.
Layout awareness including matching practices, latch-up rules, and parasitic sensitivity.
Systematic approach to design, simulation, and debug with thorough documentation habits and a personal commitment to first-silicon success.

Nice-to-haves

Experience with advanced CMOS nodes below 28nm and their analog implications.
Familiarity with inverter-based or ring-amplifier design techniques.
Knowledge of Verilog-A modeling for system-level verification.
Exposure to design-for-manufacturing practices for analog yield improvement.