Cache Architect

About the role

You will specialize in cache architecture at a semiconductor company, owning the design of the cache hierarchies that determine how effectively the processor's execution resources are fed. Cache architects live in the details of sizing, associativity, replacement policy, prefetching, partitioning, and coherency, and their decisions show up directly in benchmark scores and customer workload performance. You will model extensively, specify precisely, and tune relentlessly until the hierarchy delivers its performance targets within its power and area budgets.

What you will achieve

• Define the complete cache hierarchy for a CPU program from L1 through last-level cache, selecting sizes, associativities, latencies, and policies through exhaustive modeling across the workload suite.
• Design replacement, insertion, and bypass policies that measurably improve hit rates on real workloads, validated against both benchmarks and customer traces.
• Architect cache partitioning and quality-of-service schemes that protect latency-sensitive applications from noisy neighbors in multi-core and multi-tenant environments.
• Specify the coherency protocol interactions for your caches with the precision required for correct implementation, including all transient states and race conditions.
• Optimize the cache subsystem for power through techniques such as way prediction, selective shutdown, and activity-aware policies, quantifying savings against performance impact.
• Correlate post-silicon cache performance against model predictions, diagnosing discrepancies and improving both the design and the modeling methodology.

What you will bring

Must-haves

• 5 to 8 years of experience in cache architecture, memory subsystem design, or CPU performance modeling with shipped silicon.
• Deep knowledge of cache organization, replacement policies, prefetching techniques, and coherency protocols.
• Strong modeling skills with the ability to explore large design spaces efficiently and draw reliable conclusions.
• Understanding of SRAM array characteristics including latency, power, and area tradeoffs and how they constrain cache design.
• Familiarity with multi-core cache coherence challenges including false sharing, coherence traffic, and scalability.
• Ability to write precise microarchitecture specifications for complex cache controllers.
• Analytical rigor and patience for the detailed tuning work that separates good cache hierarchies from great ones.

Nice-to-haves

• Experience with non-inclusive or exclusive cache hierarchies and their verification challenges.
• Knowledge of emerging memory technologies and their implications for cache design.
• Familiarity with security aspects of caches including side-channel mitigations.