Block-Level Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, SVA, block-level testbenches, Synopsys VCS, Cadence Xcelium, protocol VIP, Python

About the role

You will own verification for individual RTL blocks at a fabless semiconductor company, working at the granularity where most bugs live. Block-level verification means deep, adversarial testing of a single design unit: every interface protocol, every state machine transition, every FIFO boundary condition. Your testbench surrounds one block and squeezes it until it confesses every bug, so that by the time blocks integrate at the subsystem level, the surprises are gone. You will develop an intimate understanding of your blocks' microarchitecture, knowing exactly where the designers cut corners and where the bugs are most likely hiding. The intensity you bring to block-level corner cases is what makes subsystem integration boring, which is exactly what every project wants.

What you will achieve

Deliver block-level testbenches that reach 100 percent functional and code coverage on assigned blocks, with every coverage hole either closed or formally waived.
Uncover corner-case bugs at the block level at a rate that keeps subsystem integration debug time under 10 percent of total project debug effort.
Verify all block interfaces against their protocol specifications using VIP and SVA checkers, with zero protocol violations at signoff.
Stress block corner cases (backpressure, error injection, reset during traffic, clock gating) that integration-level testing cannot reach, and document each scenario so subsystem teams understand what is already proven.
Hand off blocks to subsystem integration with clean, documented verification status so integrators inherit confidence, not risk.

What you will bring

Must-haves

2 to 5 years of block-level verification experience with SystemVerilog and UVM.
Skill in building focused, high-intensity testbenches that maximize bug-finding per simulation cycle.
Strong SVA for interface protocol checking and internal invariant monitoring.
Experience with constrained-random stimulus tuned to block-specific corner cases rather than generic traffic.
Understanding of common block structures: pipelines, FIFOs, arbiters, and register files, and where their bugs hide.
Ability to read microarchitecture specifications and derive exhaustive test scenarios from them.
Disciplined coverage analysis: distinguishing unreachable coverage from untested functionality.

Nice-to-haves

Experience with formal verification to supplement block-level simulation.
Familiarity with power-aware block verification (clock gating, retention).
Knowledge of DFT insertion effects on block-level verification.
Experience with high-speed interface protocols relevant to the block's application.