Baseband IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Baseband analog, filters, PGAs, ADC/DAC interfaces, IQ mismatch calibration, direct-conversion architectures, Cadence Virtuoso, SpectreRF

About the role

You will join a wireless semiconductor company designing the baseband analog sections of transceiver SoCs. The team owns everything between the RF front end and the digital modem: channel-select filters, programmable gain stages, and the converter interfaces that carry IQ data. This role matters because baseband linearity, noise, and IQ balance set the EVM and sensitivity the whole radio is judged on, and these blocks consume a large share of the transceiver power budget. Each wireless generation reshuffles baseband requirements, keeping the design challenges fresh. You will work shoulder to shoulder with RF and DSP engineers on every program.

What you will achieve

Ship baseband chains that meet EVM, noise figure, and linearity budgets on first silicon across gain settings and temperature
Design channel-select filters and PGAs with programmable bandwidth and gain that track across process without factory calibration where possible
Cut baseband power consumption through architecture and bias optimization while preserving dynamic range for the worst-case blocker profile
Deliver IQ mismatch calibration schemes that hold image rejection across the product's operating range in production volumes
Drive system-level budgeting with RF and digital teams, trading noise, linearity, and power to land the best overall transceiver PPA
Support modem integration and over-the-air testing, debugging baseband-related EVM and sensitivity issues on real hardware
Evaluate modulation and bandwidth demands of upcoming standards, prototyping baseband chains ahead of product need

What you will bring

Must-haves

2-5 years designing baseband or low-IF analog circuits with at least one shipped wireless product
Strong understanding of receiver and transmitter chain analysis: cascaded noise figure, IIP3 budgeting, and blocker profiles
Design experience with active filters (biquad, Gm-C), PGAs, and baseband amplifiers in CMOS
Familiarity with direct-conversion impairments: DC offset, IQ mismatch, LO leakage, and their calibration
Proficiency in Cadence Virtuoso and SpectreRF for baseband and mixed-signal simulation
Working knowledge of modulation and EVM: how circuit impairments translate to system performance
B.S. or M.S. in Electrical Engineering with an RF or analog circuits focus

Nice-to-haves

Experience with digital-assisted analog techniques: background calibration running in firmware
Familiarity with 5G, WiFi, or Bluetooth PHY requirements and test methodology
Prior work on ultra-low-power wake-up receivers or IoT radios