Bare-Metal Firmware Engineer

Firmware Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Bare-metal C development, custom startup code and linker scripts, interrupt-driven architectures, direct register-level programming, cycle-accurate timing analysis, minimal HALs, bootloader development

About the role

You will write firmware with no operating system standing between your code and the silicon: bare-metal development for products where determinism, minimal footprint, and absolute hardware control matter most. Bare-metal engineers own literally everything: startup code, interrupt vector tables, clock tree configuration, and the precise timing behavior that RTOS abstractions would obscure. You will develop an intimate, register-level understanding of your microcontroller, reasoning about clock cycles and peripheral behavior with total confidence. This is firmware in its purest and most demanding form, for engineers who want complete ownership of the machine and accept complete responsibility for it.

What you will achieve

Deliver complete bare-metal firmware systems: custom startup code, interrupt-driven peripheral drivers, and application logic with deterministic, verifiable behavior
Achieve cycle-accurate timing for critical functions through careful interrupt architecture design and measurement-validated timing analysis
Minimize resource consumption dramatically: fitting rich, capable functionality into tiny flash and RAM footprints through disciplined implementation
Build robust bare-metal software architectures: super-loop designs with hierarchical state machines or custom cooperative schedulers that stay maintainable as complexity grows
Debug confidently at the lowest possible level: custom fault handlers, register dump analysis, and instruction-level investigation when no abstractions exist to help

What you will bring

Must-haves

2 to 5 years writing bare-metal firmware in C with no RTOS involved, on products that shipped to customers
Deep microcontroller knowledge: reset and startup sequences, vector table configuration, clock tree setup, and memory-mapped peripheral programming
Experience writing and maintaining linker scripts: memory region definitions, section placement control, and bootloader-to-application handoff mechanics
Interrupt-driven design expertise: priority scheme design, reentrancy analysis, critical section management, and latency budgeting
Ability to read and understand assembly language when necessary: interpreting compiler output, debugging optimized code, and writing time-critical sections
Disciplined timing analysis habits: measuring interrupt latencies and worst-case execution paths with oscilloscopes and hardware timers
BS in Electrical or Computer Engineering

Nice-to-haves

Experience developing custom bootloaders and robust in-field firmware update mechanisms from scratch
Familiarity with MISRA C or other constrained coding standards applied to bare-metal safety-relevant code
Knowledge of advanced low-power optimization: clock gating strategies, peripheral shutdown sequencing, and sleep mode orchestration
Experience with FPGA-adjacent bare-metal work: soft-core processors or memory-mapped custom peripherals