ASIC Verification Methodologist

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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Apple

NVIDIA

Qualcomm

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Broadcom

Marvell

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The job description

Tech stack. SystemVerilog, UVM, methodology definition, testbench templates, lint and CDC flows, Python, documentation, training

About the role

You will define how verification gets done at a fabless semiconductor company, owning the methodology, templates, and flows that every verification engineer builds on. This is a methodology role, not a people-management role: your influence comes from the quality of the flows you create, the templates teams adopt, and the training that raises everyone's game. When a project starts, your testbench templates and checklists are the foundation; when a tapeout succeeds, your signoff methodology is part of why. You will measure what works, kill what does not, and evolve the flow every project cycle based on coverage data, bug data, and engineer feedback. The best methodology is the one engineers follow because it makes them faster, and building that is your craft.

What you will achieve

Define and publish the project verification methodology: testbench architecture standards, coding guidelines, and review checklists adopted by all block teams.
Build reusable testbench templates and starter environments that cut new-block bring-up time by 50 percent across the project.
Establish lint, CDC, and X-propagation flows as mandatory pre-simulation signoff steps, catching structural issues before they consume simulation cycles.
Create and deliver verification training (UVM best practices, SVA writing, coverage closure) that measurably improves new-hire ramp time.
Measure methodology adoption and effectiveness, using coverage and bug data to refine the flow each project cycle.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with strong opinions, backed by results, about how verification should be done.
Deep UVM and SystemVerilog knowledge sufficient to write the templates and base classes others build on.
Experience defining or significantly improving verification flows, checklists, or coding standards on a real project.
Familiarity with lint, CDC, and related structural verification tools and how they fit into a signoff flow.
Strong technical writing for methodology documents, guidelines, and training materials.
Ability to influence engineers across teams through the quality of your work rather than organizational authority.
Scripting skills for building the automation that makes methodology easy to follow.

Nice-to-haves

Experience evaluating EDA tools and making adoption recommendations.
Exposure to formal verification methodology and where it complements simulation.
Background in teaching, mentoring, or technical training delivery.
Experience with metrics dashboards for tracking verification quality.