ASIC Verification Engineer

About the role

You will join a fabless semiconductor company where the verification team is the last line of defense before tapeout. The team builds constrained-random UVM testbenches for high-performance ASIC blocks used in datacenter products, and this role owns the verification quality of the blocks assigned to you, from first testbench bring-up through coverage closure and final signoff. You will turn architecture specifications into verification plans, build the stimulus and checkers that hunt corner-case bugs, and partner daily with RTL designers to drive every issue to closure. The bugs you catch in simulation are bugs that never cost a silicon respin, which makes your judgment on coverage completeness and signoff readiness one of the most valuable inputs to every tapeout decision.

What you will achieve

• Ship complete UVM testbenches for assigned RTL blocks and drive functional coverage to 100 percent of the approved verification plan before RTL freeze.
• Hold nightly regression pass rates above 98 percent across suites of 2,000 or more tests by triaging every new failure within one business day.
• Reduce defect escapes to silicon by uncovering corner-case bugs with constrained-random stimulus, directed stress tests, and protocol checkers.
• Deliver bug reports with waveforms, log excerpts, and minimal reproducers that let designers land fixes within 48 hours of filing.
• Cut testbench bring-up time on each new block by 30 percent by reusing VIP agents, coverage models, and automation scripts from prior projects.

What you will bring

Must-haves

• 2 to 5 years of ASIC or FPGA verification experience writing SystemVerilog testbenches.
• Hands-on UVM experience building agents, sequences, sequencers, and scoreboards from a clean start.
• Strong SVA skills for writing interface assertions and protocol checkers that run in simulation.
• Proven ability to run, debug, and close regressions in VCS, Xcelium, or Questa on real project schedules.
• Solid understanding of functional coverage modeling and the discipline of driving coverage closure to signoff.
• Scripting fluency in Python or Perl for regression automation, log parsing, and results reporting.
• Comfort with Git-based RTL workflows, merge requests, and peer code review for testbench code.

Nice-to-haves

• Exposure to low-power verification with UPF or CPF power intent.
• Familiarity with formal property checking tools such as VC Formal or Jasper.
• Working knowledge of AMBA protocols including AXI, AHB, and APB.
• Exposure to gate-level simulation and SDF-annotated timing checks.