Analog IC Layout Engineer

Analog Design Engineer Mid-level (L4 equivalent) 2-5 years

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Qualcomm

Texas Instruments

Analog Devices

Broadcom

NXP

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The job description

Tech stack. Analog layout, Cadence Virtuoso Layout, matching and symmetry techniques, parasitic extraction, DRC and LVS, EM and IR analysis, Python and SKILL

About the role

You will create the physical layouts of analog integrated circuits at a semiconductor company, translating circuit schematics into silicon geometries where every micron affects performance. Analog layout engineers practice a discipline where artistry meets engineering: device matching, symmetry, parasitic control, isolation, and electromigration all depend on layout decisions that no automated tool can make well. Your layouts directly determine whether precision circuits meet their specifications, and designers will seek out the layout engineers whose work consistently produces working silicon.

What you will achieve

Create high-quality analog layouts for blocks such as op-amps, bandgaps, data converters, and PLLs, implementing matching, symmetry, and common-centroid techniques that deliver the required precision.
Optimize layouts for parasitic control, minimizing critical capacitances and resistances while managing coupling between sensitive nodes through careful placement and shielding.
Implement robust power distribution, guard rings, substrate isolation, and latch-up prevention, ensuring reliable operation across all conditions.
Run and resolve DRC, LVS, antenna, and density checks cleanly, delivering tapeout-ready layouts that pass physical verification without last-minute scrambles.
Perform parasitic extraction and back-annotation, working with designers to evaluate layout impact on circuit performance and iterating where needed.
Collaborate closely with circuit designers throughout the layout process, understanding the circuit's sensitivities well enough to make independent layout decisions that protect performance.

What you will bring

Must-haves

2 to 5 years of experience in custom analog or mixed-signal IC layout with taped-out products.
Deep understanding of analog layout principles: matching, symmetry, common-centroid, interdigitation, and dummy structures.
Proficiency with Cadence Virtuoso Layout XL and physical verification tools for DRC, LVS, and extraction.
Knowledge of latch-up prevention, ESD structures, guard rings, and substrate noise isolation techniques.
Understanding of electromigration rules and current-density-aware routing for analog power distribution.
Ability to read schematics and understand circuit operation well enough to anticipate layout sensitivities.
Craftsmanship and patience for the meticulous work that distinguishes excellent analog layout.

Nice-to-haves

Experience with advanced process nodes and their layout challenges including double patterning.
Familiarity with high-speed or RF layout techniques including transmission line structures.
Scripting skills in SKILL or Python for layout automation and parameterized cells.
Knowledge of reliability mechanisms such as NBTI, HCI, and their layout implications.