Analog IC Design Engineer

About the role

You will join a fabless semiconductor company as a generalist analog IC design engineer on the mixed-signal team. The team builds the analog front ends, references, and data converters that sit inside the company's flagship SoCs, and every new product generation asks more of this team than the last. This role matters because product performance is set in the analog domain: your circuits define the power budget, noise floor, and measurement accuracy the whole product ships with, and customers benchmark the company on exactly those numbers.

What you will achieve

• Ship at least two production tapeouts per year, owning analog blocks from schematic entry through post-layout verification, review signoff, and silicon validation
• Hit power, noise, and bandwidth targets on first silicon, keeping re-spins of your own blocks to zero across a full release cycle
• Reduce design iteration time by building reusable testbenches and parameterized cells that cut setup time for new blocks roughly in half
• Deliver measurement correlation reports that close the loop between simulation and lab data, turning discrepancies into model and testbench updates for the next tapeout
• Own your blocks through customer bring-up and field debug, diagnosing silicon anomalies and shipping ECOs that restore full datasheet compliance
• Contribute to the team's design review culture by presenting your blocks clearly and catching issues in peers' designs before they reach layout

What you will bring

Must-haves

• 2-5 years designing analog blocks in a CMOS process, with at least one shipped production chip that credits your circuit work
• Deep command of feedback theory, noise, distortion, and stability analysis applied to real circuits, not just textbooks
• Fluency in Cadence Virtuoso schematic entry and Spectre simulation, including process corners, Monte Carlo, mismatch, and worst-case analysis
• Working knowledge of layout effects that constrain your floorplan: device matching, parasitic capacitance, latch-up rules, and ESD structures
• Comfort at the bench with oscilloscopes, spectrum analyzers, and source meters to validate and debug your own silicon
• Disciplined documentation habits: design specs, review decks, and validation reports that let others pick up your work cleanly
• B.S. or M.S. in Electrical Engineering or a closely related field

Nice-to-haves

• Experience with behavioral modeling in Verilog-AMS for system-level and top-level simulation
• Familiarity with digital timing and STA concepts so your analog-digital interfaces close cleanly at tapeout
• Exposure to automotive or industrial qualification flows, such as AEC-Q100 or extended temperature characterization
• Prior work with precision references, temperature sensors, or on-chip oscillators that broadened your circuit portfolio