Advanced Nodes Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, 3nm and below process awareness, variation-aware verification, low-power signoff at advanced nodes, aging/reliability checks, multi-patterning-aware flows

About the role

You will verify designs targeting advanced process nodes (3nm and below) at a semiconductor company where physics intrudes on functionality: variation shifts timing, low voltages invite new failure modes, and signoff complexity multiplies. Working with designers and process-aware backend teams, you will adapt verification to catch the bugs that only exist at these geometries: marginal timing paths, voltage-droop sensitivity, and reliability mechanisms that change behavior over the chip's lifetime. Your verification closes the gap between ideal RTL and real silicon at the leading edge.

What you will achieve

Deliver variation-aware verification strategies that prove functionality across process corners, voltage, and temperature extremes defined for the target node.
Drive signoff on timing-marginal logic by verifying correct behavior under modeled variation, in partnership with STA and physical design teams.
Ship verification of advanced-node-specific features: aggressive power gating, dynamic voltage scaling, and on-chip variation sensors, all proven in simulation.
Cut late-stage surprises by identifying node-specific verification gaps (ECO risks from dense routing, EM-aware constraints) before they reach the backend.
Reduce reliability risk by verifying aging and degradation mechanisms (NBTI, HCI effects on timing margins) wherever the design models them.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with at least one tapeout on an advanced node (7nm or below).
Strong SystemVerilog/UVM skills with experience in rigorous, checklist-driven signoff flows.
Understanding of how process variation, low-voltage operation, and parasitics affect functional behavior, not just timing.
Experience with multi-corner verification thinking: why a design passes at TT but fails at SS or FF corners, and how to prove it.
Familiarity with low-power verification (UPF) as practiced at advanced nodes, including fine-grained power domains.
Ability to collaborate with physical design, STA, and reliability engineers on node-specific verification requirements.
Healthy paranoia about margins: at advanced nodes, the pass/fail line is thinner, and your tests respect that.

Nice-to-haves

Experience with 3nm-class specifics: backside power delivery implications or gate-all-around device behavior.
Knowledge of functional safety or automotive-grade reliability verification at advanced nodes.
Familiarity with ML-driven or analytics-driven verification triage for large regression volumes.
Exposure to chiplet or 3D integration verification challenges.