Advanced Node Mixed Signal Engineer

About the role

You will design analog and mixed-signal circuits in advanced finFET nodes at a fabless semiconductor company pushing its products to 5nm and below. The team confronts everything that makes advanced-node analog hard: low supply headroom, layout-dependent effects, self-heating, and parasitics that dominate at these geometries. This role matters because the company's flagship products live or die on whether analog works at these nodes, and you will make it work. You will work directly with the foundry on PDK and model issues, and your hard-won knowledge of node-specific failure modes will become the team's advanced-node playbook for future tapeouts. You will also document the node-specific failure modes in the team's advanced-node playbook, so each tapeout benefits from every hard lesson the previous one taught.

What you will achieve

• Ship analog/mixed-signal blocks (ADCs, PLLs, high-speed I/O, or references) in 7nm or below with first-silicon success despite low headroom and aggressive parasitics.
• Drive headroom-constrained design by mastering low-voltage circuit techniques: inverter-based amplifiers, body-bias-assisted design, and stacked-device strategies that hold gain and swing at 0.75V and below.
• Reduce layout-dependent-effect impact by owning LDE-aware design: characterizing and compensating for LOD, WPE, and fin quantization effects in your blocks before tapeout.
• Own self-heating and EM sign-off for your blocks: thermal-aware simulation where needed and EM-clean routing verified against foundry rules at advanced-node current densities.
• Cut advanced-node respins by building a checklist of node-specific failure modes (antenna at thin metals, density effects, voltage-dependent capacitance) and closing every item before tapeout.

What you will bring

Must-haves

• 2-5 years of analog/mixed-signal design with at least one tapeout in a finFET node (16nm or below; 7nm or below preferred).
• Deep understanding of finFET device behavior: quantized widths, reduced headroom, gate leakage, self-heating, and back-bias limitations.
• Experience with layout-dependent effects: LOD, WPE, STI stress in finFET layouts and how to design and lay out against them.
• Fluency in advanced-node sign-off: EM/IR at high current densities, antenna rules, density and double-patterning-aware layout review.
• Low-voltage analog design skills: maintaining gain, linearity, and swing with supplies at or below 0.8V.
• Lab bring-up experience on advanced-node silicon, including correlating measurement to LDE-sensitive simulation.

Nice-to-haves

• Experience at 5nm or 3nm (gate-all-around awareness).
• Knowledge of backside power delivery and its analog implications.
• Familiarity with digital-assisted analog techniques (calibration-heavy architectures suited to advanced nodes).