ADC/DAC IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SAR, pipeline, and delta-sigma architectures, ENOB, SFDR, SNR optimization, comparators, DAC arrays, calibration, Cadence Virtuoso, Spectre, MATLAB modeling

About the role

You will join a data-converter company designing ADCs and DACs that define the measurement and signal fidelity of customer systems. The team spans architectures from low-power SAR to high-speed pipeline to precision delta-sigma, each tuned for its market. This role matters because converter performance (ENOB, SFDR, power per conversion) is the headline spec on every datasheet, and customers select vendors on exactly those numbers. Converter figures of merit improve slowly and expensively, so architectural insight matters more than brute force.

What you will achieve

Ship converters that meet or beat datasheet ENOB, SFDR, and SNR targets on first silicon across the full temperature range
Drive architectural choices (SAR vs pipeline vs delta-sigma) from system requirements, landing the best figure of merit for each product's power budget
Design calibration and trimming schemes that recover yield lost to mismatch, lifting effective resolution by multiple bits in production
Cut power per conversion step through comparator, amplifier, and switching optimization validated against measured silicon
Build MATLAB and Python behavioral models that predict converter performance before transistor-level design, de-risking architecture decisions early
Own converter characterization in the lab with coherent sampling and FFT analysis, closing the loop between measured spurs and circuit root causes
Track competitor converter benchmarks and keep the roadmap ahead on the metrics customers actually compare

What you will bring

Must-haves

2-5 years designing data converters with at least one shipped ADC or DAC product
Deep understanding of converter architectures: SAR, pipeline, flash, and delta-sigma, including their error sources and tradeoffs
Fluency in dynamic performance metrics (ENOB, SFDR, SNR, THD) and how circuit nonidealities map to each
Design experience with key sub-blocks: comparators, capacitive DAC arrays, residue amplifiers, or decimation filters
Proficiency in Cadence Virtuoso and Spectre, including transient-noise and periodic analyses for converter simulation
Behavioral modeling skills in MATLAB or Python for architecture exploration and verification
B.S. or M.S. in Electrical Engineering with a mixed-signal or data-converter focus

Nice-to-haves

Experience with background calibration, dithering, or mismatch-shaping techniques
Familiarity with high-speed sampling front ends and input driver co-design
Prior work on precision or audio converters where dynamic range dominates the design