Yield Enhancement Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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Intel

TSMC

Samsung

Micron

Applied Materials

GlobalFoundries

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The job description

Tech stack. yield pareto analysis, inline defect data, wafer sort data, Klarity/Exensio or equivalent, defect source tracing, kill-ratio analysis, Python/SQL

About the role

A semiconductor manufacturer runs a dedicated yield team whose only metric is good die out per wafer start, and you will be one of the engineers who moves that number. You will mine sort, probe, and inline data to find the biggest yield loss mechanisms, then drive fixes with process and equipment teams until the pareto changes shape. This role converts data into yield points, and every point you recover flows directly to gross margin.

What you will achieve

Drive yield improvement projects that add a cumulative 3 points of line yield per year on your assigned products, with each project tracked from hypothesis through verified silicon results.
Build weekly yield paretos that rank loss mechanisms by die impact and convert them into prioritized action plans the whole engineering organization can execute against.
Reduce systematic yield loss by correlating inline defect data to sort bins, focusing effort where kill ratios exceed 10 percent and ignoring noise that does not kill die, and focusing engineering hours where the return is highest.
Own yield-learning-vehicle test chip analysis, identifying new failure signatures within 48 hours of sort data availability so learning keeps pace with production.
Cut time-to-root-cause on yield excursions from weeks to days through standardized data pipelines, reusable analysis templates, and clear escalation criteria.

What you will bring

Must-haves

BS or MS in electrical engineering, materials science, physics, or statistics, with strong quantitative training.
2 to 5 years in yield engineering, process integration, or semiconductor data analysis with wafer-level datasets.
Strong SQL or Python skills for wafer-level data analysis and correlation, including spatial pattern recognition on wafer maps.
Experience with yield management systems such as Klarity, Exensio, or yieldWerx for pareto generation and bin analysis.
Working knowledge of semiconductor fabrication flow and failure mechanisms, so data patterns connect to physical causes.
Ability to present findings to engineering and management audiences with clear recommendations and expected yield impact.

Nice-to-haves

Machine learning experience applied to defect or yield prediction, including model validation on fab data.
Knowledge of design-for-manufacturing and test-chip design for yield learning.
Familiarity with e-beam inspection or voltage-contrast techniques for defect confirmation.