Vector Unit Design Engineer

About the role

You will design vector processing units for CPUs at a semiconductor company, implementing the wide SIMD datapaths, lane interconnects, permute networks, and predication logic that accelerate AI, HPC, and media workloads. Vector unit designers build some of the widest, most power-hungry structures in the processor: hundreds of parallel lanes operating in lockstep at high frequency, with complex interactions between element widths, predication, and exception handling. Your designs determine how effectively the CPU handles the dense math that increasingly dominates modern computing.

What you will achieve

• Design vector execution datapaths including multi-lane ALUs, permute and shuffle networks, reduction trees, and format converters, meeting aggressive timing targets across all supported element widths from bytes to double-precision.
• Implement predication, masking, and fault-suppression logic for vector operations, handling the intricate control interactions between vector execution and the scalar exception model correctly.
• Design vector register files and lane interconnects balancing read and write bandwidth, power consumption, and area for the target vector length and microarchitecture.
• Optimize vector units for power efficiency through fine-grained clock gating, lane shutdown, and activity-aware techniques, since wide datapaths otherwise dominate the block power budget.
• Verify vector functionality exhaustively across element widths, predication patterns, tail handling, and edge cases including faults occurring partway through vector operations.
• Support performance validation of vector-heavy workloads, confirming the unit delivers its expected speedups on ML inference, HPC kernels, and media processing pipelines.

What you will bring

Must-haves

• 5 to 8 years of experience in vector, SIMD, datapath, or high-performance logic design with shipped silicon.
• Deep understanding of SIMD microarchitecture: lane organization, shuffle and permute networks, predication models, gather-scatter, and their hardware implementation.
• Strong SystemVerilog design skills for very wide, timing-critical datapaths with complex control interactions.
• Knowledge of vector ISA extensions such as Arm SVE, RISC-V V, or x86 AVX, including their software ecosystem and hardware implications.
• Timing closure experience on wide datapath structures with aggressive cycle-time requirements.
• Rigorous verification discipline for the combinatorial explosion of vector corner cases across widths, masks, and operations.
• Power optimization skills for wide, high-activity logic including fine-grained gating strategies.

Nice-to-haves

• Experience with matrix or tensor datapath extensions for ML acceleration.
• Familiarity with ML workload characteristics, quantization, and dataflow implications.
• Knowledge of GPU SIMT execution models for comparative architectural insight.
• Exposure to variable-length vector architectures and their unique design challenges.