UVM Verification Engineer

About the role

You will be the UVM methodology specialist on the verification team of a fabless semiconductor company, owning the depth and quality of the UVM environments the whole project builds on. While other engineers focus on features and coverage, you focus on the machinery: layered sequence libraries, register models, scoreboard architectures, and reusable agents that make every testbench faster to build and easier to debug. Teams across the project adopt your components because they are the best-built pieces of the environment. You will set the standard for how UVM is written here, review the testbench code that others produce, and solve the methodology problems (configuration, reuse, performance) that slow everyone down. When the project's verification scales cleanly instead of collapsing under its own complexity, your architecture is why.

What you will achieve

• Deliver a reusable UVM agent library (drivers, monitors, sequencers) adopted by at least three block teams, cutting their environment development time in half.
• Build layered sequence libraries that generate legal, corner-case, and error-injection traffic, raising constrained-random bug-finding effectiveness measurably.
• Implement UVM register models with functional coverage on register access sequences, closing register-related coverage to 100 percent.
• Architect scoreboards with reference models that catch data-path mismatches within one transaction of the error, minimizing debug time per failure.
• Reduce testbench code duplication across the project by 40 percent through shared base classes, configuration objects, and factory overrides.

What you will bring

Must-haves

• 2 to 5 years of verification experience with deep, hands-on UVM development beyond basic testbench usage.
• Expert understanding of UVM phases, the factory, configuration database, TLM ports, and objection mechanisms.
• Proven ability to write layered sequences, virtual sequences, and sequence libraries for complex protocols.
• Experience building UVM register models (RAL) including backdoor access, coverage, and register sequences.
• Strong scoreboard design skills with transaction-level modeling and reference model integration.
• SystemVerilog OOP fluency: inheritance, polymorphism, and parameterized classes applied to testbench architecture.
• Experience integrating third-party UVM VIP and resolving agent configuration issues.

Nice-to-haves

• Familiarity with the UVM-ML or multi-language verification for mixed SystemVerilog and SystemC environments.
• Experience with portable stimulus (PSS) for cross-platform test reuse.
• Knowledge of formal methods to complement UVM-based dynamic verification.
• Experience profiling and optimizing simulation performance of UVM environments.