System-on-Chip (SoC) Hardware Engineer

Hardware Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SoC evaluation and integration, reference design adaptation, power delivery for SoCs, high-speed memory interfaces, board support packages, JTAG debug, power sequencing, clock architectures

About the role

You will design the hardware platforms built around complex SoCs: application processors, wireless combo chips, and AI accelerators that define modern products. SoC hardware engineers own everything the silicon vendor does not: power trees, memory subsystems, clocking, and the board-level integration that determines whether the chip performs to its datasheet or disappoints. You will work from reference designs but never blindly, validating every assumption with simulation and measurement because vendors optimize for their demo board, not your product. Deep datasheet literacy and healthy skepticism are your most valuable skills.

What you will achieve

Design SoC carrier boards and system hardware with correct power sequencing, clock distribution, and memory interfaces validated by measurement
Deliver successful first-silicon or new-SoC bring-up: power validation, boot debugging, and interface functional testing completed on schedule
Adapt vendor reference designs intelligently, understanding which elements are critical to preserve and which can be optimized for cost or form factor
Characterize SoC power consumption across operating modes, driving accurate battery life or thermal models the product team can plan against
Debug complex SoC-level issues spanning power, signal integrity, and firmware interaction with systematic cross-domain analysis

What you will bring

Must-haves

2 to 5 years designing hardware around complex SoCs or application processors with products that shipped to customers
Understanding of SoC power architectures: core rails, sequencing requirements, DVFS behavior, and power state transitions
Experience with high-speed memory interfaces including LPDDR4/5 and DDR4, covering layout constraints and training validation
Familiarity with reading SoC datasheets and hardware design guides critically, identifying gaps, errors, and hidden risks
Lab skills for SoC debug: JTAG boundary scan, power rail measurement under dynamic load, and boot failure analysis
Knowledge of clock architectures: crystal selection, PLL configuration, and jitter requirements for high-speed interfaces
BS in Electrical Engineering or Computer Engineering

Nice-to-haves

Experience with AI accelerator or NPU integration: power delivery for high transient loads and thermal solution design
Familiarity with secure boot hardware requirements: fuse programming, tamper detection, and secure element integration
Knowledge of MIPI interfaces including CSI and DSI and their board-level implementation challenges
Experience with module-based designs using systems-on-module and custom carrier board development