Subsystem Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. SystemVerilog/UVM, subsystem integration, AMBA interconnect verification, multi-clock verification, use-case driven testing

About the role

You will verify subsystems at a semiconductor company: the clusters of IP blocks (a memory subsystem, an I/O subsystem, a compute tile) that sit between individual blocks and the full SoC. Working with the designers of every block in your subsystem, you will prove they work together: data flows end to end, clocks and resets interact correctly, and the subsystem meets its performance targets. Your signoff de-risks SoC integration before it starts, and your use-case tests are the closest thing to the real product before software arrives.

What you will achieve

Deliver subsystem-level testbenches that exercise end-to-end data paths across all blocks in the subsystem, from ingress to egress, under realistic traffic, with transaction tracking that attributes every failure to its source block.
Drive use-case coverage (typical and worst-case traffic profiles) to the targets in the verification plan, validated with subsystem architects and updated as the design evolves.
Ship integration bug finds spanning block boundaries (protocol mismatches, FIFO sizing errors, clock-domain issues), each driven to RTL closure with the responsible designers.
Cut SoC bring-up risk by verifying clock, reset, and power interactions at the subsystem level before full-chip integration begins.
Reduce performance surprises by measuring subsystem throughput and latency against the architecture budget and flagging shortfalls while there is still time to fix them.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with block-level ownership and meaningful integration exposure.
Strong SystemVerilog/UVM skills applied to multi-block environments and system-level scenarios, not just single DUTs.
Understanding of interconnect protocols and integration concerns: address decoding, arbitration, QoS, and backpressure behavior.
Experience verifying designs with multiple clock domains and reset domains interacting in non-trivial ways.
Ability to coordinate debug across several block designers, keeping shared issues moving to closure without letting them bounce.
Systems thinking: you reason about data flow, buffering, and resource contention, not just single-block behavior.
Diplomacy with persistence: integration bugs belong to everyone and no one, and you drive them home anyway.

Nice-to-haves

Experience with performance modeling or traffic generation for interconnect analysis.
Familiarity with subsystem-level power intent verification.
Knowledge of NoC architectures and their verification challenges.
Exposure to virtual platforms or hybrid verification for early subsystem testing.