Semiconductor Integration Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. module integration, process flow design, inline metrology, cross-module interactions, split lots, technology qualification, FMEA

About the role

A wafer fab needs an integration engineer to own how process modules combine into a working technology, the systems-level view that no single module owner can provide. You will design process flows, manage split lots that answer the critical integration questions, and resolve cross-module interactions that only appear when the full flow runs together. You make the whole flow greater than the sum of its parts, and when a new technology misses its targets, you are the engineer who figures out why.

What you will achieve

Deliver integrated process flows for new technology nodes that hit parametric targets on first full-loop silicon, through careful module interface design and pre-silicon risk review.
Drive split-lot execution plans that answer key integration questions within 6 weeks of lot start, with clear hypotheses, success criteria, and decision points for every split.
Reduce module-to-module interaction escapes by 40 percent through structured interface reviews held before any module change reaches the integrated flow, with sign-off from affected module owners.
Own technology qualification lots, shepherding them from first silicon through characterization to production release on schedule, with no surprise gaps at release review, and with all qualification criteria documented and met.
Cut flow-level cycle time by identifying and eliminating redundant steps and metrology, removing coverage that adds time without reducing risk, and streamlining the critical path from lot start to qualification.

What you will bring

Must-haves

BS or MS in electrical engineering, materials science, chemical engineering, or physics.
2 to 5 years in process integration, module ownership, or technology development with full-flow exposure.
Deep understanding of full CMOS process flows from FEOL through BEOL, including how module choices propagate to device behavior.
Experience designing and analyzing split-lot experiments with statistical rigor and clear go/no-go criteria.
Ability to coordinate across lithography, etch, deposition, implant, and CMP teams, aligning competing priorities into one flow.
Strong technical writing for process flow documentation and qualification reports that auditors and customers can trust.

Nice-to-haves

TCAD flow simulation experience for pre-silicon integration risk assessment.
Knowledge of advanced node integration challenges for FinFET and gate-all-around architectures.
Experience with technology transfer between fabs, including flow matching and gap analysis.