RTOS Embedded Software Engineer
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The job description
Tech stack. C, FreeRTOS, Zephyr, ThreadX, ARM Cortex-M/R, priority-based scheduling, IPC primitives, memory protection (MPU), trace tools (Percepio/Tracealyzer)
About the role
You will join an industrial controls company whose real-time platforms manage motion, safety interlocks, and process control with hard deadlines. The RTOS team owns scheduling architecture, inter-task communication, and the deterministic behavior the entire product depends on. This role matters because when deadlines are measured in microseconds, the operating system is not plumbing: it is the product's most critical correctness property.
What you will achieve
- Ship a Zephyr-based firmware platform supporting 40+ concurrent tasks with verified worst-case scheduling latency under 5 microseconds, proven by trace capture on production hardware, with latency histograms published for every release
- Drive adoption of memory protection (MPU) partitioning across the task set, eliminating an entire class of cross-task corruption bugs as confirmed by a full quarter with zero such incidents
- Reduce priority-inversion incidents to zero by redesigning shared-resource protocols around priority inheritance and ceiling disciplines, verified by stress testing under maximum load
- Build a deterministic IPC framework (message queues, event flags, stream buffers) that cuts inter-task communication defects by 45% year over year, measured across all firmware teams using the platform
- Own real-time trace and profiling infrastructure, giving every team member deadline-miss root-cause data within minutes of a failure instead of days of guesswork
What you will bring
Must-haves
- 2-5 years building firmware on a real-time OS such as FreeRTOS, Zephyr, ThreadX, or embOS in production products
- Deep understanding of priority-based preemptive scheduling: context switch cost, tick overhead, priority inversion, and its remedies
- Fluency with RTOS IPC primitives and their failure modes, including queue overflow, semaphore misuse, and deadlock
- Experience with interrupt design: ISR length budgets, deferred processing strategies, and nested interrupt handling
- Working knowledge of MPU/MMU-based task isolation on Cortex-M or Cortex-R, including region configuration
- Ability to measure and prove timing: GPIO-toggle analysis with a logic analyzer, trace tools, and WCET estimation
- Strong C with disciplined avoidance of dynamic allocation in real-time paths and ISRs
Nice-to-haves
- Experience porting an RTOS to a new MCU or writing a board support layer from scratch
- Familiarity with safety-certified RTOS variants or qualification kits and what the qualification evidence requires
- Knowledge of multicore AMP configurations with inter-core communication and shared-memory protocols
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