Principal Mixed Signal Design Engineer

About the role

You will set the analog technical direction across product lines at a fabless semiconductor company whose roadmap depends on mixed-signal differentiation. Principal engineers here do not just design blocks; they decide which circuits the company invests in, which architectures die, and how the analog craft gets institutionalized. This role matters because your architecture calls will shape two to three years of tapeouts, and your ability to make hard tradeoffs early will save the organization from late, expensive respins.

What you will achieve

• Define the analog architecture roadmap for two to three product generations, choosing circuit topologies and technology nodes against power, performance, cost, and schedule with written tradeoff analyses.
• Drive first-silicon success across the analog portfolio: own the sign-off methodology (corners, Monte Carlo yield targets, EM/IR, reliability) that every team follows, and review every major analog tapeout.
• Deliver at least one breakthrough block per year that moves the competitive needle: record FoM on a converter, 2x jitter improvement on a clocking block, or a new calibration scheme that removes an external component.
• Cut analog-related respin rate by institutionalizing failure-mode learning: post-silicon reviews that turn every silicon surprise into an updated checklist, model, or design rule for the whole org.
• Build the analog bench: hire and mentor senior and staff designers, run rigorous design reviews, and create the training material that turns good designers into independent block owners.

What you will bring

Must-haves

• 12+ years of analog/mixed-signal design with a long record of successful tapeouts in multiple technology nodes, including at least one advanced node.
• Recognized depth in at least two analog domains (data converters, PLLs, high-speed I/O, RF front ends, power management, or precision analog).
• Demonstrated org-wide technical leadership: setting methodologies, killing bad architectures early, and being the reviewer other teams call before tapeout.
• Track record of mentoring senior engineers and raising the bar through design reviews, not just through your own designs.
• Expert-level understanding of device physics, mismatch, noise, and layout-dependent effects, applied to real silicon tradeoffs.
• Experience working with foundries on PDK issues, model accuracy, and process-option selection.

Nice-to-haves

• Published papers or patents in analog/mixed-signal design.
• Experience across multiple foundries and process options.
• Familiarity with chiplets or 2.5D/3D integration and its analog implications.